Capacitive power transfer (CPT) do not produce eddy current effects and are concentrated between plates. To increase the capacitance of CPT coupler and satisfy the charging demands of loads, a novel coupler and its associated compensation network are proposed. The coupler elevate the equivalent capacitance to nanofarad-scale. The compensation network designed in this paper can achieve input zero phase angle (ZPA) and load-independent constant-voltage (CV) output. Experimental results demonstrate that the designed coupler's equivalent capacitance is several times greater than that of traditional structures. The compensation network successfully meets the requirements for input ZPA, CV output, and anti-misalignment performance.

Accurate modeling of self-heating effect in power transistors is crucial for reliable design and performance evaluation of wireless communication circuits and systems. This letter presents an enhanced time delay neural network (TDNN) technique specifically developed to model power transistors considering self-heating effect. At first, an enhanced TDNN model topology suitable for power transistors is proposed. To accurately describe the self-heating effect, a thermal sub-circuit is incorporated into the model framework. Moreover, novel formulations for direct current, small-signal S-parameters, and large-signal harmonic balance outputs of the proposed TDNN are derived so that typical measurement data can be utilized for model training. Finally, training algorithm is also proposed to effectively optimize the weighting and thermal parameters in the proposed TDNN model. The effectiveness of the proposed technique is validated through a modeling example involving a practical power transistor. The resulting TDNN model is embedded in Keysight Advanced Design System, and simulation results based on this model demonstrate good agreement with the measured data.

This brief presents an ultra-low voltage (ULV) charge pump (CP) topology with high power conversion efficiency (PCE) designed for ultra-low supply voltage, low-power on-chip applications. The proposed ULV-CP employs a combination of dynamic gate-bias (DGB) and forward body-bias (FBB) techniques with the objective of enhancing overdrive voltage and reducing conduction losses, thereby enabling operation at ultra-low voltage. A 4-stage ULV-CP has been designed and implemented in a 22-nm FD-SOI process. Measurement result shows that it can reach a peak PCE of 83.87% at a supply voltage of 0.36 V. Compared to other CP circuits, the proposed circuit outperforms in terms of PCE, maximum output power, and minimum supply voltage.

This letter introduces a method to optimize the temperature offset drift and noise efficiency factor (NEF) for chopper and auto-zero instrumentation amplifiers. In order to optimize offset drift and NEF, our proposed amplifier exploits a threshold voltage (Vth) tracking reference. A prototype of the proposed amplifier was fabricated using a standard 0.35μm complementary metal oxide semiconductor technology and occupies 0.174 mm2. Using the Vth tracking reference, an offset drift of 80 nV/℃ is achieved. The measured NEF was 2.45 with a supply current of 1.1 mA.

This work presents a 32 Gb/s tunable equalizer implemented in 65 nm CMOS. The design combines an active inductor CTLE with NCC and a source-follower buffer, overcoming the gain-bandwidth trade-off of traditional CTLEs while maintaining stable behavior under PVT variations with a DC gain variation of 5.6 dB. A 2-tap full-rate DFE further suppresses residual ISI. The results show that the proposed equalizer compensates for a 29 dB channel loss at the 16 GHz Nyquist frequency. It achieves an eye opening of 204 mV vertically and 0.77 UI horizontally at 32 Gb/s NRZ. The post-layout area is only 0.0015 mm². Furthermore, with a power consumption of only 4.6 mW, the equalizer achieves an exceptional energy efficiency of 0.14 pJ/bit.

This paper presents an autonomous bias-flip rectifier (BFR) integrated with an on-chip flip switch timing controller (FSTC) designed for piezoelectric energy harvesting. The proposed FSTC utilizes a pulse-width modulation (PWM)-based feedback loop that automatically calibrates the switch control pulse width, thereby eliminating the need for post-fabrication trimming and allowing the circuit to adapt to component variations. Implemented in a 0.18-μm CMOS process, the circuit achieves fully autonomous operation and can successfully cold-start from a piezoelectric harvester’s open-circuit voltage of 2 V. Measurement results confirm that the FSTC effectively optimizes the bias-flip timing, thereby maximizing the harvested power. Compared to an ideal full-bridge rectifier (FBR), the proposed BFR achieves up to 3.2× higher output power. These results demonstrate the effectiveness of the proposed on-chip automatic calibration architecture in realizing high-efficiency and cost-effective vibration energy harvesting systems.

Data-retention flip-flop (DRFF) efficiently maintains data during sleep mode and retains state during transitions between active and sleep mode. This paper proposes a novel source-biased stacked inverter (SBS-Inverter) and a low-leakage, structure-reused DRFF. The sleep latch circuit constructed using the SBS-Inverter can effectively reduce the power of DRFF when storing data. Reuse of the structure improves the situation of redundant transistors in certain DRFF. Fine-grained inverter level optimization reduces delay and power during the active mode. The DRFF was implemented using a 55 nm process and subjected to comprehensive analysis. Post-layout simulation results at a supply voltage of 0.4 V indicate that the proposed DRFF’s data retention leakage power is only 5.3 pW. At a supply voltage of 0.8 V, the power-delay product is only 0.146 nW*ns@20 MHz. Monte Carlo simulation results considering process, voltage and temperature (PVT) variations show that the proposed DRFF can operate reliably down to a supply voltage of 0.4 V.

This paper presents a broadband inductor-less CMOS receiver architecture that eliminates on-chip inductors while maintaining wideband impedance matching and acceptable noise performance. The proposed receiver integrates an inductor-less low-noise amplifier (LNA) and an active mixer to achieve compact implementation and reduced parasitic sensitivity; the LNA employs a combined common-gate and common-source topology with a noise-cancellation scheme under a current-reuse configuration, and a modified Gilbert-cell mixer performs single-ended to differential conversion with controllable conversion gain without passive baluns. Designed in a 0.18-µm CMOS technology with a 1.8-V supply, post-layout simulation results demonstrate broadband operation from 0.4 to 2 GHz, achieving a conversion gain of 14.2-17.2 dB and a noise figure of 11.5-13.8 dB with the measurement buffer enabled, while the intrinsic front-end exhibits a minimum noise figure of 6.55 dB. The proposed architecture provides a practical trade-off among bandwidth, noise performance, linearity, and power consumption for highly integrated broadband RF front-end applications.

Complex ordinary differential equations (ODEs) are vital for scientific computations. This paper presents a Reconfigurable High-precision Complex ODE Solver (RHCOS) on FPGA with high area-efficiency. The RHCOS efficiently integrates Runge-Kutta and Adams algorithm by reconstructing the recursive structures through unified computing units and dynamic coefficient switching. Additionally, a cyclic update cache mechanism is introduced to reduce memory accesses and latency. Experimental results show that, for solving six-degree-of-freedom spatial dynamics equations, the RHCOS achieves a 14.1× speedup over software solution at 200 MHz, with high area-efficiency and an order of 10-6 for relative computational error.