ABSTRACT This article features a comprehensive methodology for analyzing and optimizing PWM dead time in automotive traction inverters, applicable to a wide range of power devices, including Si IGBT/Diodes, SiC MOSFETs, and Si/SiC Fusion switches. The proposed methodology enables a systematic comparison of dead time characteristics, focusing on part‐to‐part tolerances and operating point‐dependent influence factors. Three traction inverter systems, each in the 200–300 kW class at 470 V, were built up utilizing Si IGBT/Diode, SiC MOSFET, and Si/SiC Fusion switches from the latest automotive‐released technology. The impact of PWM dead times on power losses was experimentally investigated for all three inverter systems, supporting the analytical model. Key findings from the experimental data include: (1) PWM dead times can account for more than 10% of the total inverter power losses in high current density SiC MOSFET inverter designs operating at typical automotive switching frequencies of 10 kHz; (2) Optimizing PWM dead times in Si/SiC Fusion power modules leads to up to a 5% reduction in total inverter power losses and improved current sharing, resulting in lower thermal stress—This was evaluated using thermal infrared measurements from the Si/SiC Fusion inverter prototype; 3) Optimized PWM dead times can reduce total harmonic distortion at light load conditions by up to 2%–3% for IGBT/Diode and up to 4%–5% for SiC MOSFET and Si/SiC Fusion inverter systems; (4) A sensitivity study in addition revealed that Si/SiC Fusion switches exhibit the most stable dead time settings under parameter variations. The benefit of optimized versus conventional 2 PWM dead times would result in an annual energy saving of approximately 6 GWh per 1 million vehicles. This highlights the significance of optimized PWM dead times in automotive traction inverters operating at typical switching frequencies of 10 kHz. The goal of this investigation is to support the development of reliable and efficient automotive traction inverters, with the methods presented being applicable to other applications as well.

ABSTRACT This paper presents a new converter solution for powering switched reluctance motors. This solution extends the capabilities of the previous C‐dump converter solution. A parallel configuration of the C‐dump capacitor connection with the power source was used. The converter has been expanded with a circuit for returning energy from the capacitor to the power source. This circuit operates by measuring the capacitor's C‐dump voltage. It allows the capacitor charging voltage to be maintained within a given range, improving the motor's operating conditions and protecting the capacitor from overcharging. This article presents a drive model and measurement verification of the simulation results. The characteristics of the presented drive are presented and compared to those of a drive without a capacitor discharge circuit. The proposed converter expands the drive's application range to include devices requiring regenerative braking. The drive is characterised by improved tolerance to control angle changes and accelerates transition processes. A drive with this converter allows for greater power and rotational speed compared to a drive with a typical converter composed of asymmetric H‐bridges.

ABSTRACT Switching devices, the most vulnerable component within converters, underscores the critical need to enhance their reliability and prolong the power converter's lifetime. This paper proposes a multi‐state reliability model for insulated gate bipolar transistors (IGBTs) that departs from conventional two‐stage models with constant failure rate. Moreover, it quantifies the effect of DC‐link voltage on IGBT reliability for switching frequencies below 5 kHz and derives an operating voltage ratio envelope of about 60% of the rated voltage. Operating within this band maximises lifetime and reduces maintenance cost, providing a practical voltage reference for control strategies. Finally, Monte Carlo simulations across multiple cases verify the feasibility and robustness of the proposed model and comparative hardware experiments support the underlying thermal assumptions of the proposed model.

ABSTRACT Three‐level neutral point clamped (3L‐NPC) converters have significant advantages in high‐voltage and high‐power applications. As a core component, IGBTs are prone to power loss under complex operating conditions, leading to increased junction temperature and reduced device lifespan. Traditional modulation methods often result in distorted current and increased harmonics, thereby raising the thermal load. To address this issue, this paper proposes a power loss reduction PWM (PLRPWM) strategy for 3L converters. This strategy seeks a balance among output harmonic suppression, reduced switching loss, and neutral point potential balance to achieve multi‐objective optimisation at low switching frequencies. Experimental and simulation results show that the PLRPWM strategy can effectively reduce power loss and harmonic distortion while maintaining stable neutral point potential, significantly enhancing the performance and operational reliability of the converter.

ABSTRACT This paper presents an experimental evaluation of a PWM modulation strategy based on reconstructed modulators applied to a seven‐level cascaded multilevel inverter. The proposed approach aims to achieve effective energy balance among inverter cells while maintaining high output voltage quality and low digital implementation cost by shifting the balancing mechanism from the carrier level to the modulation stage through the reconstruction of sinusoidal modulating signals. The performance of the strategy is analyzed under variations of the modulation index, considering key performance indicators such as total harmonic distortion, weighted total harmonic distortion, power imbalance among inverter cells, and FPGA resource utilization. Experimental results demonstrate that optimal performance is achieved at a modulation index of m = 0.9, where THD and WTHD values of 1.34% and 1.05% are obtained, respectively, while the maximum power imbalance among cells remains below 1%, reaching 0.64%. A comparative evaluation with level‐shifted PWM strategies confirms that the proposed approach provides improved harmonic performance and significantly reduced digital resource usage, requiring only 11% of the available FPGA resources. These results highlight the effectiveness of the reconstructed modulators strategy as a practical and efficient solution for cascaded multilevel inverters in photovoltaic and other energy conversion applications.

ABSTRACT This paper investigates the application of Finite Control Set Model Predictive Control (FCS‐MPC) for high‐performance speed regulation of Brushless DC (BLDC) motors under dynamic operating conditions. The study addresses the challenge of precise tracking for complex references, including sinusoidal, square, triangular, and sawtooth waveforms essential for advanced applications such as robotic and hydraulic actuator systems in aerospace applications. A key contribution is the analytical investigation of the predictive cost function, which elucidates the trade‐off between inverter switching frequency and tracking accuracy. This analysis identifies an optimal weighting factor that enables a ∼55% reduction in switching frequency while maintaining dynamic tracking errors below 0.5 RPM. For experimental validation, a custom BLDC motor drive was designed and implemented using an ESP32 processor, incorporating a novel bidirectional torque‐limiting strategy for operational safety. Both simulation and experimental results confirm that the proposed approach achieves accurate dynamic speed control for frequencies up to 0.3 Hz. Furthermore, a comparative study demonstrates the superiority of the method, showing an 85% reduction in amplitude error compared to a conventional PWM‐ON strategy for a 0.3 Hz sinusoidal reference.

ABSTRACT Submodule (SM) failure is one of the key factors leading to instability in modular multilevel converter (MMC) systems. To address this challenge and enhance system reliability, redundant configurations have become the core solution. However, existing redundancy strategies cannot simultaneously balance the transient repair speed and steady‐state output accuracy. Hence, a novel fusion redundant control scheme that combines cold‐standby and hot‐standby redundancy strategies is proposed to overcome the challenge of optimizing both transient repair speed and steady‐state output accuracy. First, an MMC structure is proposed, which is equipped with both cold‐standby SMs and hot‐standby SMs and realizes the sharing of cold standby SMs. Then, the casting and switching strategies of the SMs are designed based on this structure. Finally, a bridge arm reference voltage update module is designed to avoid the voltage offset caused by the coordination of the cold‐standby module and the hot standby module. Simulation and experimental results confirm that the proposed method effectively addresses both transient and steady‐state performance issues, facilitates rapid repairs, and ensures precise and reliable operation of the MMC system after a fault event.

ABSTRACTThis paper presents a novel fault‐tolerant approach for cascaded H‐bridge inverters with a full‐bridge single‐phase rectifier cell structure. Upon a fault, the faulty cell is disconnected from the circuit, and the inverter switches from normal operation (symmetric mode) to faulted operation (asymmetric mode). In asymmetric mode, one of the full‐bridge single‐phase rectifier cells in the faulty phase transitions from a full‐bridge to a half‐bridge configuration. The level‐shift pulse‐width modulation (PWM) is employed during symmetric mode, while a modified level‐shift PWM is utilized in asymmetric mode. The inverter's output power and voltage remain unchanged during faults in the modified PWM method. Additionally, the performance of the proposed fault‐tolerant algorithm is evaluated and validated using results from simulations and an experimental prototype of a seven‐level inverter.

ABSTRACTIn photovoltaic power generation applications, multiple low‐voltage PV modules must be boosted and connected in parallel for high power output. However, due to the variability of PV energy input, the parallel DC‐DC converter modules often operate under asymmetric conditions, which deteriorates bus voltage ripple and reduces system stability and component lifespan. To address these issues, this paper proposes an optimal phase‐shift modulation method with asymmetric phase shifts to effectively suppress the ripples at the point of common coupling of parallel‐connected converters. To do so, a model for the output voltage ripple of boost and buck–boost parallel converter is established using the equivalent small parameter method (ESPM) with the optimal phase‐shift angle determined by this modulation approach. Furthermore, a triple‐loop current‐sharing control strategy is implemented to ensure current sharing among the modules, enhancing the overall ripple suppression capability of the proposed modulation technique. Simulation and experimental results indicate that this integrated approach significantly improves the performance and stability of parallel converter systems.

ABSTRACT This paper implements low‐cost GaN‐based three‐phase voltage and current sources to validate power protecting relays. This proposal develops a voltage generator that uses three single‐phase full‐bridge converters equipped with an LC filter and an isolating transformer. It also includes a current generator using three single‐phase half‐bridge converters furnished with an LCL filter. Both voltage and current testing sources are assembled employing GaN transistor technology, which enables operation at high switching frequencies and passive filters with low‐value components. Experimental tests are conducted to confirm and validate the operation and dynamic performance of voltage and current testing sources. Finally, the performance of the voltage and current signal generator is assessed by testing a commercial protection system (SEL‐451) through directional current function. This is achieved by emulating a fault condition, where three voltage and current signals are generated to trigger the trip signal after surpassing the relay threshold.