Machine learning models have been applied to a wide range of computational lithography applications since around 2010. They provide higher modeling capability, so their application allows modeling of higher accuracy. Many applications which are computationally expensive can take advantage of machine learning models, since a well trained model provides a quick estimation of outcome. This tutorial reviews a number of such computational lithography applications that have been using machine learning models. They include mask optimization with OPC (optical proximity correction) and EPC (etch proximity correction), assist features insertion and their printability check, lithography modeling with optical model and resist model, test patterns, and hotspot detection and correction.

Gradient Boosted Tree is a powerful machine learning method that supports both classification and regression, and is widely used in fields requiring high-precision prediction, particularly for various types of tabular data sets. Owing to the recent increase in data size, the number of attributes, and the demand for frequent model updates, a fast and efficient training is required. FPGA is suitable for acceleration with power efficiency because it can realize a domain specific hardware architecture; however it is necessary to flexibly support many hyper-parameters to adapt to various dataset sizes, dataset properties, and system limitations such as memory capacity and logic capacity. We introduce a fully pipelined hardware implementation of Gradient Boosted Tree training and a design framework that enables a versatile hardware system description with high performance and flexibility to realize highly parameterized machine learning models. Experimental results show that our FPGA implementation achieves a 11- to 33-times faster performance and more than 300-times higher power efficiency than a state-of-the-art GPU accelerated software implementation.

This paper presents experimental evaluations of operating speed, power consumption, and chip temperature under various load conditions on commercial FPGAs. To measure the operating speed of FPGAs, we count the oscillation frequency of a ring oscillator (RO), which is implemented on one 4-input look-up table (LUT). The load condition on FPGAs can be controlled by the number of activated ROs in parallel around the measurement RO. The measurement results show that operating speed may be decreased more than10% with 142 ROs as load circuits and the degradation rates depend on the measurement location in an FPGA. The evaluation of die-to-die variations using four more FPGA boards show that there exists a non-negligible speed variation.

On behalf of the editorial board, I am pleased to present the thirteenth volume of the IPSJ Transactions on System LSI Design Methodologies (TSLDM).TSLDM aims to provide the best opportunity for all researchers in the field of the design, the electronic design automation, and the methodologies of system LSIs or systems-on-a-chip to publish and learn about state-ofthe-art works.TSLDM covers various aspects of system LSIs or systems-on-a-chip design methodology, including design experience, architecture, synthesis, modeling, simulation, verification, testing, embedded software, emerging applications, and so on.The thirteenth volume will consist of the February and August issues as usual.Each issue will contain an invited paper written by top researchers in the world as well as peer-reviewed papers.Our peer-reviewed papers are classified into three types: Regular, Short and Survey.A regular paper is a description of research that is academic or technical in nature or products of development which is valuable to members of the IPSJ from the viewpoints of novelty and usefulness.A short paper is a brief description of research that is academic or technical in nature or products of development which is valuable to members of the IPSJ from the viewpoints of novelty and usefulness.A survey paper is a description of technical trends or perspectives that are organized, classified and/or evaluated from author's own viewpoint which contains useful information for members of the IPSJ.As an open-access online journal, TSLDM allows authors to disseminate their excellent works to our research community easily.Every paper can be accessed anytime anywhere.

A conversion method of a netlist consisting of conventional logic gates for superconducting rapid single flux quantum (RSFQ) circuit realization is proposed. The method detects OR gates which can be replaced with confluence buffers (CBs) which converge their input pulses into their outputs. The detection problem of replaceable OR gates is treated as a SAT problem. Each OR gate requires clock input in RSFQ circuits. By replacing OR gates with CBs, wiring for clocking those OR gates are eliminated and the number of active devices known as Josephson junctions is reduced.

Hardware verification requires a lot of effort. A recent study showed that on average, there are more verification engineers working on a project than design engineers. Hence, one of the biggest challenges in design and verification today is to find new ways to increase the productivity. For software development the agile methodology as an incremental approach has been proposed and is heavily used. Behavior Driven Development (BDD) as an agile technique additionally enables a direct link to natural language based testing. In this article, we show how BDD can be extended to make it viable for hardware design. In addition, we present a two-fold strategy which allows to specify textual acceptance tests and textual formal properties. Finally, this strategy is complemented by methods to generalize tests to properties, and to enhance design understanding by presenting debug and witness scenarios in natural language.

Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from “classical 2D chips” to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

In advanced technology nodes, unidirectional layout is strongly preferred for high-density metal layers for better manufacturability.The lithography printing of unidirectional layout can be tightly controlled with illumination source optimization and resolution enhancement techniques.Meanwhile, with the unidirectional layout, self-aligned double and quadruple patterning can be applied to achieve finer pitches beyond the resolutions limits of 193 nm lithography tools.However, unidirectional layout style introduces significant impacts on the physical design flow.Notably, unidirectional routing limits the standard cell pin accessibility, which makes manual cell layout design and optimization more and more challenging under modern standard cell architecture.In the routing phase, routing densities and resource competitions on lower metal layers are becoming increasingly high, where intelligent approaches are needed to resolve routing resource competitions for unidirectional routing closure.Moreover, post-routing optimization is inevitable to avoid significant engineering-changing-efforts for unidirectional routing under advanced manufacturing constraints.In this paper, we present a holistic approach, including standard pin access evaluation/optimization, pin access and routing co-optimization and post-routing optimization, to enable unidirectional routing closure in advanced technology nodes.

In recent printed circuit board (PCB) design, due to the high density of integration, the signal propagation delay or skew has become an important factor for a circuit performance. As the routing delay is proportional to the wire length, the controllability of the wire length is usually focused on. In this research, a heuristic algorithm to get equal-length routing for disordered pins in PCB design is proposed. The approach initially checks the longest common subsequence of source and target pin sets to assign layers for pins. Single commodity flow is then carried out to generate the base routes. Finally, considering target length requirement and available routing region, R-flip and C-flip are adopted to adjust the wire length. The experimental results show that the proposed method is able to obtain the routes with better wire length balance and smaller worst length error in reasonable CPU times.