Abstract In order to form a compartmental EMI shielding structure for radio frequency (RF) modules, we have proposed the new process named ”imprint-Through Mold Via (i-TMV)”, which could be fabricated by imprinting with a silicon master and filling with conductive paste. In this work, a test coupon was fabricated and EMI shielding effect of the i-TMV was actually evaluated by measurement of the electric field strength that leaked through from via array. As a result, it was found that the shielding effect was 23.6 dB at 4 GHz, which was close to the completely shielded value with a metal cap (25.6 dB). This result indicated that the i-TMV was significantly effective as a compartmental EMI shielding for the Sub-6 band application.

Abstract The experimental study described herein investigates thermomigration of both eutectic Sn/Pb and lead free Sn/Ag/Cu solder joints, with the additional focus on the development of an Arrhenius failure model of time-to- failure as a function of temperature. Flip chip test vehicles were assembled with daisy chain die, with and without underfill, attached to ceramic and organic package substrates, using standard reflow processes. Three different under bump metallurgy technologies were investigated: sputtered thin film Al/NiV/Cu, thick electroplated nickel, and thick electroplated copper (i.e., copper pillars). The test vehicles were subjected to unbiased high temperature storage (HTS) testing with temperatures ranging from 125°C to 200°C. Failure was determined from continuity testing at regular intervals until an open circuit or high resistivity was detected. The results demonstrate the robustness of Al/NiV/Cu UBM at temperatures less than 130°C, and of the thick electroplated UBM at temperatures of 150°C. Based on the HTS test results, and corresponding analyses, a thermomigration failure model was generated for eutectic Sn/Pb and lead free Sn/Ag/Cu solder alloys using an Arrhenius-like fit to the failure data.

Abstract Most fluxes and their flux residue are corrosive, and their presence on the surface of assemblies may cause reliability concerns due to electrochemical migration. This study firstly refers to the test method IPC-TM-650 2.3.32D and 2.6.15C and the requirements in J-STD-004A to evaluate flux-induced corrosion and the corrosivity of their flux residue. Then thermogravimetric analysis is used to evaluate the flux residue level after soldering under identical conditions. These comparison data can be utilized to compare flux performance of solder pastes. For the cleanliness evaluation after flux cleaning, the qualitative analysis refers to IPC-A-610G and adopts optical inspection to observe the flux cleaning effect. The quantitative analysis refers to IPC-TM-650 2.3.28B ion chromatography test method to analyze the level of ionic species after flux cleaning. In addition to IPC-TM-650 2.3.28B ion chromatography method, the effectiveness of other methods has been well demonstrated to characterize the fluxes and their flux residue in clip bonding assembly.

Abstract Heterogeneous integration is considered as the key technology to create large, complex System in Package (SiP) assemblies of separately manufactured, smaller components. Proper control of the uniformity of each process step constitutes one of the main challenges during integration of the different components into a higher-level assembly. In this context, processes that create thick layers by electrochemical deposition are especially susceptible to variations across the substrate. Such processes include copper pillar and bump as well as tin-silver applications. Insufficient coplanarity of electrolytic copper would result in significant reliability issues or evolution of stress in the package. Upcoming hybrid bump designs with features of different dimensions pose additional challenges to the electrolytic copper and tin-silver processes. Purposeful adjustment of differences between the heights of pillars of different diameters may be required after the copper process step in order to obtain the best uniformity for the complete stack with tin-silver on top. In addition to coplanarity, the electrolytic process should allow modification shape of the individual pillar or bump. In this context, a versatile copper electrodeposition process will be discussed that allows adjustment to a broad variety of uniformity parameters and combinations thereof. In combination with suitable tin-silver deposition processes, this process is expected to significantly improve the reliability of copper pillars and bumps for advanced packaging applications.

Abstract In this study, the reliability of chiplets heterogeneous integration on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the thermal cycling test and drop test of the structure. The test results are plotted into Weibull distributions, where the Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope interval and the true characteristic life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the chip/package assembly of the heterogeneous integration package are provided and discussed.

Abstract Increasing demands for storage and high-performance memory in applications such as artificial intelligence (AI), machine learning and processing storage are driving long-term growth in the market. This paper will highlight the key challenges encountered in packaging next-generation memory devices and discuss some of the technological developments required to address them while considering performance, cost, and yield. An evaluation is highlighted of a remote microwave plasma process to remove damage caused by laser ablation during the wafer dicing process that shows an improvement in die strength using this process.

Abstract 172-lead (16x16 mm body size) and 100-lead (10x10 mm body size) MAXQFP's and 172 MAXQFP_EP (exposed pad) for automotive industry are introduced. The advantage of MAXQFP as compare to standard LQFP/QFP packages will be outlined. Thermal & mechanical simulation results were performed to prove its advantage over conventional LQFP and LQFP_EP. The challenges in manufacturing, designs and concerns of tighter lead pitches for MAXQFP are briefly addressed. Methods and data to resolve these challenges will be shown. For example, Sn whisker and Sn migration both are concerns to MAXQFP because of smaller distance between adjacent leads. The board-level solder joint reliability (SJR) has been collected to prove it is AEC G1 compliant. Visual inspection methods and requirements on AOI (automatic object inspection) systems on solider joints of J-leads of MAXQFP for are proposed. Standard AEC G1 component level reliability stresses defined at AEC Q100 which are TC (temperature cycling), HTSL (high temperature storage life), THB (Temperature Humidity Biased) and uHAST (un-biased HAST) tests are summarized Since Cu wires were used, AEC Q006 data are also collected. Assembly challenges are described. Future works will be summarized.

Abstract High value devices used in microwave modules and other microelectronic assemblies have become increasingly thin and susceptible to “Component Out Of Pocket” (COOP) conditions that can occur during packaging, shipping, and customer handling. This defect condition is especially problematic for automated assembly which strives to be touch-free and efficient with orderly device presentation. COOP is a major contributor to “Cost Of Poor Quality” (COPQ) within the business. A funded study into COOP conditions was conducted and a dozen root causes were identified. It was discovered that traditional “waffle packs” have mechanical issues related to flatness tolerances with respect to the waffle tray and lid. The addition of a standard clip further contributes to the issue, both of which are key root causes of the costly “Component Out Of Pocket” (COOP) condition. A novel Lid-Clip System (LCS2) was engineered to compensate for those mechanical issues, bringing robust captivation and preservation of devices in waffle tray pockets. Static dissipative material for lid and clip was selected to provide unparalleled ESD Class 000 protection for high value devices with the lowest voltage susceptibility thresholds.

Abstract Ultrasonic heavy wire bonding is a standard process in packaging technologies of power semiconductor modules. Due to increasing demands on reliability of the electrical contacts under high temperature loads, copper wires with significantly better electrical and thermal properties compared to aluminum are used more often nowadays. This results in new challenges in process development due to higher process forces and ultrasonic power; for this purpose, a simulation model has been developed to improve process development. The process model is based on a co-simulation with sub-models for the different physical phenomena. The sub-models are based on parameters, which need to be identified from measurements. This contribution focusses on the identification of the material model. Therefore, a method is presented, which allows for an iterative identification of the stress-strain characteristics from compression tests based on a modified tensile-compression machine. In compression tests under ultrasonic load, the bond wire material behavior under ultrasonic load is investigated to characterize the so-called ultrasonic-softening-effect. The simulation model with identified model parameters is then used to predict main-effects-diagrams for aluminum and copper wire bond processes on DCB. The simulation results are validated by comparison to results from parameter studies of ultrasonic heavy wire bonding experiments.

Abstract With the miniaturization of integrated circuit technology and process, chips are getting smaller and smaller, and thus it results in fan-out packaging with RDL process was derived to extend the ball grid array design space. The applicable range of RDL now includes products in the fields of Networking, HPC, AI and even SiPh. And the new package types comprised of the RDL process include e-WLB, chip first FOCoS, chip last FOCoS, FO-PoP and 2.5D IC etc. The total pin count in FOCoS packaging can be more than ten times than that the pin counts in a large FCBGA packaging; the FOCoS package layout density can reach tens or even hundreds of times than FCBGA. High density and complex connectivity in FOCoS cause more difficult using traditional EDA tool for packaging design. In addition, the RDL process manufacturing equipment is different from that for traditional packaging substrate and it is more like the foundry process, so it is required to consider design rule check and LVS check flow compatible to IC design flow except for the package layout. It is necessary to have different methods and tools from that in the past to complete a reliable design. In this paper, there is an introduction about the new design flow and platform for high density package design and it describes the new design platform could overcome the difficulties of layout on high-density packages such as FOCoS. And then talking about FOCoS Assembly Design Kit (ADK) to provide to the IC or system designers, especially the new design rule checking tools and procedure, as well as example about how DRC tools plays an important role in RDL process improvement and design. In addition to checking the design rule for the layout, verifying the interconnections between the components in the package after design is very important to FOCoS packaging which is generally used in multiple dice integration such as homogeneous and heterogeneous integration design.