Abstract This paper describes major contributing factors to the CPI risk and reveals the mitigation strategy successfully applied jointly by GLOBALFOUNDRIES as the silicon supplier and Qualcomm Technologies, Inc., as the customer responsible for packaging. This strategy involves thermo-mechanical modelling, data collection on wafer level using shear test to assess the BEoL-stability, Cu Pillar process development and optimization. The qualification of these process changes had been completed and implemented in volume production. The paper also discusses mechanical wafer level and thermo-mechanical package modeling approaches. A model has been applied to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow process. These factors include for instance the Cu Pillar bump geometry and stack up. The results of the modelling work were used to set up experiments to further mitigate CPI related failure modes in BEoL on the package level. GLOBALFOUNDRIES and Qualcomm Technologies, Inc., assessed Cu Pillar design related rules such as Cu Pillar diameter and height as well as the Cu Pillar stack up. Process improvements were carried out to reduce the undercut of the barrier underneath the Cu Pillar. The paper reveals how effectively an optimized Cu Pillar design and improved Cu Pillar processing can contribute to the risk mitigation of CPI failure modes in the BEoL for critical package designs and assembly processes with low margin against BEoL fracture during solder reflow. Furthermore, process improvements applied to enhance the BEoL stack strength were investigated and have been implemented in high-volume production. A strong correlation was established between data collected on wafer level to assess the BEoL strength and data collected on package level.

Abstract With the advancement in miniaturization, the die is getting thinner and the solder bump is getting smaller for BGAs. Consequently, the thermal warpage is getting more severe due to coefficient of thermal expansion mismatch between die and molding compound, and often resulted in non-wet-open (NWO) at BGA assembly. NWO has been ailing the industry for a long time, and costly rework is required to remove the problem. In this study, a “cold-welding barrier” method has been developed in suppressing NWO. At BGA assembly, after printing solder paste onto PCB, the BGA bumps are dipped into creamy flux prior to placing onto paste printed. This flux pickup will effectively suppress NWO by serving as cold-welding barrier. A low activity flux is considered having as wider reflow profile window than a medium activity flux. Alternatively, the solder bump of BGA can be pre-coated with solid flux at packaging house. The effect of solid-flux coating is equally effective in suppressing NWO. As cold welding barrier, both no-clean flux and water soluble flux are considered physically effective. However, a water soluble flux should not be used together with a no-clean solder paste based on compatibility and reliability consideration. Furthermore, only no-clean solid flux is recommended for solder bump coating purpose, mainly based on moisture pickup issue associated with water soluble flux.

Abstract MOCVD (Metal-Organic Chemical Vapor Deposition) copper metallization was developed on 300mm wafers, to fulfil 3D Through-Silicon Via (TSV) interconnect requirements. Using a fluorine-free organometallic precursor, the bis(dimethylamino-2-propoxy)copper (II) Cu[OCHMeCH2NMe2]2 at low temperature deposition, we developed a high purity, low stress copper film with strong adhesion to a TiN barrier layer. Argon was used as a carrier gas and H2 and/or H2O as a co-reactant. This MOCVD technique offers good conformality observed with 10μm×120μmTSVs. The thin copper seed layer was successfully integrated on 300mm wafers. A new XRD protocol was developed to characterize the copper seed layer along the TSV sidewalls, revealed higher microstructure quality, lower stressed in the case of copper film deposited by CVD compared to those deposited by i-PVD.

Abstract This work describes a new type of formaldehyde-free electroless copper electrolyte that can be used for a broad set of applications and materials, especially for the processing of next-generation substrates. The plating solution was successfully applied in both, a laboratory and production-scale environment. The results have been evaluated in detail and were benchmarked against a formaldehyde-based reference. A characterization of the obtained metal films was carried out by different analytical techniques, including microscopy, X-ray fluorescence (XRF), scanning electron microscopy (SEM), adhesion tests and non-blister verification. Additionally, studies concerning chemical bath stability, throwing power and electrical reliability have been made. Based on the obtained data we believe that the current achievements represent a suitable technology to replace formaldehyde in existing printed circuit board (PCB) production without loss of process performance and thus provide a sustainable “green” alternative to the industry.

Abstract This paper details an architecture that includes a recess in motherboard (RiMB) to enable increased packaging density of functional components for next generation mobile personal computing products. The recess depth, manufacturing methods, and SMT assembly data are included to provide the reader with a full overview of the manufacturing and assembly challenges.

Abstract As mobility products, such as smart phones, tablets and wearable devices, continue on the paths of both miniaturization and high performance, components and packaging are likewise driven to become smaller and thinner. In mobile devices, a thinner package is required, especially for the Application Processor and memory combination. The Package-on-Package structure can achieve module thinness by embedding a die (or dies) into a package and is thus attractive for reducing the height of an AP. The Die-Embedded and RDL structure has been in development as a package corresponding to POP structure. This structure has two characteristics of manufacturing method, based on the substrate manufacturing process. One is the RDL-first process, whereby the RDL is manufactured before die attachment. This process decreases the die loss from defects in the RDL formation. The other method is to manufacture the packages in panel form instead of wafer form. The key features of this structure are panel-form manufacturing and via connection between the substrate and the top-RDL. In IMAPS 2016, the Die Embedded and RDL structure on i-THOP®, which was used as the substrate was reported. The die-to-die inter connection was fabricated on i-THOP® for a 2.1D application. Both the die attachment and the RDL formation were successfully performed. The reliability tests proceeded. The results indicated that the i-THOP® with the Die Embedded and RDL structure can be applied to packaging of AP in mobile devices. The next challenge is to make a smaller package using the Die Embedded and RDL structure. To decrease the package area, a finer-pitch via connection that was less than the design rule of 200μm was evaluated. For reduction of package thickness, a thinner substrate, approximately 160μm thickness, was applied. The new test sample with these improvements was designed and proceeded to evaluation. The dimensions of the sample are 15 × 15 mm2 size and 340μm thickness (without solder ball), a 100μm-thick die was embedded and a one-layer of RDL was formed on the die. In this development, the warpage of the thin substrate after die attachment might be large, so there is an issue of package warpage and the handling of a thin substrate. In this report, results of low warpage structure design and development status of fine via connection formation are described.

Abstract Thin-film capacitors can be created on various substrates including glass, low-temperature co-fired ceramic (LTCC), and potentially on laminate PC board materials if the surface is sufficiently smooth. This paper looks at the circuit-design issues of how such a technology could be used in high-speed digital and microwave circuits for improving both signal integrity and power integrity (SI/PI). Two primary applications are examined: the formation of a low-inductance power-supply bypass allowing reduced supply ‘noise’, and the formation of AC coupling (DC blocking) circuits with improved signal return-loss.

Abstract With the trends towards miniaturization and heterogeneous integration, both IC and advanced substrate manufacturers are striving to meet the needs of next generation platforms, to increase the density of interconnects, and generate conductors featuring finer lines and spaces. Advanced manufacturing technologies such as Semi-Additive-Processing (SAP) and Advanced Modified-Semi-Additive-Processing (amSAP) were devised, realized and implemented in order to meet these requirements. Line and space (L/S) requirements of copper conductors will be below 5/5μm for advanced substrates, with 2/2μm L/S required for chip to chip connections in the near future. Herein we report about the performance of the new developed ferric sulfate based EcoFlash™ process for SAP and amSAP application with the focus on glass as the substrate and VitroCoat as thin metal oxide adhesion promotion layer. The adhesion promotion layer (about 5–10 nm thickness) is dip-coated by a modified sol-gel process followed by sintering which creates chemical bonds to the glass. The sol-gel dip coating process offers good coating uniformity on both Though-Glass-Via (TGV) and glass surfaces under optimized coating conditions. Uniform coating can be achieved up to aspect ratios of 10:1 by using a 300μm thick glass with 30μm diameter TGV. The thin adhesive layer enables electroless and electrolytic copper plating directly onto glass substrates. Excellent adhesion of electroless plated copper seed layer on glass can be achieved by using the adhesive layer and annealing technology. The thin adhesive layer is non-conductive and can be easily removed from the area between circuit traces together with the electroless copper seed layer by etching with a ferric sulfate based process. We have successfully integrated the adhesion layer and electroless and electrolytic copper plating technologies into semi-additive process and seed layer etching capable producing L/S below 10 μm.

Abstract This works describes a promising method for rapid prototyping tape stencils for the application of solder paste. This process is appropriate for research settings requiring developmental flexibility and the ability to deal with small device dies. This work compares the volume of solder paste deposited versus aperture volume for several common tape materials and several common printed circuit board (PCB) stencil materials. The solder deposits are then reflowed to identify which aperture and solder paste parameters can generate successful solder bumps. Electrically conductive solder bonds for small bond pads (100 μm and larger) are demonstrated between silicon device dies and glass dies using this process.

Abstract Silicon interposers represents an interesting alternatives to organic packages for the fabrication of complex System In Package (SIP) modules especially for RF application. Among the advantages of this technology are the capability to fabricate fine-pitch redistribution layers and also to embed high quality passive components inside the interposer. This allows the passive components to be very close to the active chips resulting in highly integrated and high performance systems. To keep the technology at a reasonable cost these last add-on features need to be fabricated with no or minor additional process steps that the ones needed for the fabrication of the interposer itself. In this work we present the design and the fabrication of various design of planar and 3D inductor devices fully compatible with the realization of a silicon interposer that is used to host an RF transmitter system operating in the 0.4 to 1 GHz frequency range. The inductors are built using two thick levels of copper RDL, on both sides of a high resistive silicon substrate and connected by through silicon via-last (TSV-last). This later doesn't require additional metallization to be realized. A dedicated test vehicle was designed to study various inductor types including planar spirals, 3D solenoids and 3D torus. To facilitate the design work, parameterized cells were built for each type of inductors. The structures geometry are designed and optimized, using electromagnetic simulator, to target inductance values in the range of 0.5 to 10 nH while addressing a quality factor greater than 20. The second part of the paper focuses on the process used to build the test vehicle, especially the realization of thick copper RDL layers on both sides of the interposer silicon wafer and the TSV-last module. Physical and DC electrical characterizations are presented to assess the integrity of the individual technology modules like thick copper RDL and TSV. The last part of the work is dedicated to the electrical characterization of the inductor devices in the targeted RF frequency range. Experimental results are presented and discussed in order to give some insight on the impact of the different design parameters on the performances of the inductors.