Switching lattices are two-dimensional arrays composed of two or four-terminals switches organized as a crossbar array. The idea of using regular two-dimensional arrays of switches for Boolean function implementation was proposed by Akers in 1972. Recently, with the advent of a variety of emerging nanoscale technologies, lattices have found a renewed interest. Emerging technologies allow more complex function integration, thanks to their smaller sizes and advanta geous properties such as zero leakage current, capability to retain data when in power-off state, and almost unlimit edendurance, to name just a few appealing features. Also, implementation of new computing paradigms combining memory and logic becomes possible. However, emerging technologies show a non-negligible defect ratio and higher sensitivity to process and environment variations. The reliability challenges in adopting these technologies need to be investigated. In this paper, we analyze the resilience of switching lattices to stuck-at-fault model (SAF). We first identify the critical switches through an elaborated sensitivity methodology and extensive analysis of the lattice. Next, we propose several techniques to improve lattice resilience in the face of these types of faults, that can be implemented after lattice logic optimization steps.

In 3D IC, wrapper chains can span across vertical directions which causes the increase in number of TSVs(through-silicon-vias)(which is used to interconnect different cores in the vertical directions). Excessive use of TSVs in wrapper design causes routing congestion and additional overhead in manufacturing. Therefore, optimization of wrapper length and judicious use of TSVs are the focus of 3D wrapper architecture design. In this work, we first propose a heuristic procedure to determine the placement of wrapper elements in several layers of 3D SOC for a number of wrapper chains and interconnect them using available number of TSVs such that the length of the longest wrapper length (LWL) is minimized. Then we apply particle swarm optimization (PSO) based metaheuristic approach on the results obtained in first case to determine the placement of wrapper chains and interconnect them using minimum number of TSVs such that the length of LWL is minimized. We compare our results with earlier works and the experimental results show the efficacy of our algorithm.

On top of the wear-out failures and external particle interventions, voltage scaling to mitigate the power consumption in multiprocessor makes cache more vulnerable to cell failures. For the indispensable voltage reduction to prolong the battery life of handheld devices, fault tolerance techniques are extremely important to ensure fault free execution in near-threshold voltage. Several fault tolerance techniques have been proposed and the remapping based techniques are found to be effective to address the issue of fault tolerance in single core systems. This work proposes an analytical model for remapping based fault tolerance techniques to evaluate the effectiveness of such schemes in multicore systems. The metrics Expected Miss Ratio in Multicore (EMRMC) and Expected Latency Ratio in Multicore (ELRMC), are introduced to characterize the behavior of remapping based techniques. The EMRMC and ELRMC are defined as the function of probability of cell failure (Pfail), block size, number of cores and threads. The system is simulated in Multi2sim 5.0, a multicore CPU-GPU simulator. The values of the metrics for different configuration parameters like probability of cell failure, number of cores, number of blocks, block size and number of threads are analysed for framing the guidelines of system configuration to deliver better performance in remapping based fault tolerance. It is observed that the EMRMC is proportional to Pfail and block size but inversely proportional to the number of cores and threads and it is not affected by the number of blocks. On the contrary, the ELRMC is inversely proportional to Pfail and block size and proportional to the number of cores and threads. It is also observed that the ELRMC is independent of the number of cores and blocks. EMRMC is best minimized for Pfail ≤ 1e-4, block size ≤ 64 bytes, number of cores ≥ 4 and number of threads ≥ 2. On the other hand, ELRMC is best observed for Pfail ≤ 1e-4, block size ≥ 64 bytes, number of cores ≥ 4 and number of threads 2.

Model-Based Testing (MBT) is a well-known technique that employs formal models to represent reactive systems’ behavior and generates test cases. Such systems have been specified and verified using mostly Finite State Machines (FSMs). There is a plethora of test generation algorithms in the literature; most of them are based on graphs once an FSM can be formally defined as a graph. Nevertheless, there is a lack of studies on analyzing cost and efficiency of FSM-based test generation algorithms. This study compares graph-based algorithms adopted to generate test cases from FSM models. In particular, we compare the Chinese Postman Problem (CPP) and H-Switch Cover (HSC) algorithms with the well-known Depth-First Search (DFS) and Breadth-First Search (BFS) algorithms in the context of covering all-transitions and all-transition-pairs criteria in an FSM. First, a systematic literature mapping was conducted to summarize the methods that have been adopted in MBT, considering FSMs. Second, the main methods found were implemented and analyzed on randomly-generated FSMs, as well as real-world models that represent embedded systems of space applications. To make comparisons, we considered analyses in terms of cost (time), efficiency (mutant analysis) and characteristics of the generated test suites (number of test cases, average length of test cases, largest and smallest test cases, standard deviation and distribution of test cases). In general, CPP presented the best results in terms of number of test cases and test suite size. In addition, CPP also presented low distribution of average length compared to other algorithms.

Logic locking is a protection technique for outsourced integrated circuit (IC) designs that thwarts IC piracy and IC counterfeiting by untrusted foundries. In this technique, the IC design house locks the correct functionality of the circuit using a key that is known only to the trusted entities in the design house. As the correct key values are provided by the design house after production, a malicious adversary in the foundry house will not be able to unlock overproduced or counterfeit ICs. In this paper, we mount linear approximation attacks and differential attacks on random logic locking (RLL), fault-analysis based logic locking (FLL), and strong logic locking (SLL) techniques. We present a formal approach to mount the linear approximation attack on multiple circuit partitions and thereafter combining the approximations to form the attack on a locked logic cone of the circuit. We present our results on ISCAS’85 benchmark circuits. In linear approximation attack, the combinatorial blocks are partitioned and expressed as linear expressions to derive a relation between the primary inputs and the primary outputs of the circuit. The attack aims to determine the linear approximation that has the highest probability of occurrence for the correct key input. In differential attacks, we could recover the embedded secret key in device with attack effort lesser than exhaustive search attack.

Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs - there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. The results demonstrate the importance to have methods both to select the test flow and design the test architecture.

This paper presents possible designs for high speed error tolerant adder using Gate Diffusion Input (GDI) technique. The 1-bit modified full adder (MFA) proposed in [1] is implemented using GDI technique (GDI-MFA). The GDI-MFA is extended to implement a 16-bit high speed error tolerant adder (GDI-HSETA). The performance of various configurations is studied based on metrics such as delay, area and power dissipation. The circuits have been simulated using pSPICE software. From the results it is observed that the proposed GDI-MFA has 52% less transistor count and consumes 33% less power compared to conventional adders. Results of simulation of GDI-HSETA and other adders in pSpice indicate that the proposed adder has 21.6% power reduction and 13% less transistor count. Also, based on the implementation of GDI-HSETA and existing 16-bit adders on FPGA Spartan 6 platform, it is observed that GDI-HSETA achieved power reduction compared to 16-bit adders using conventional design.

The outsourcing business model is dominating the semiconductor industry. Due to this loss of control over the design flow, several threats have become a major source of concern, including overproduction and IP overuse. For over a decade, several solutions have been proposed in the literature to counteract such threats. These solutions consist in hiding the behavior of the IPs/ICs until the design house securely unlocks them. This way, only unlocked IPs/ICs can be used properly while locked ones produce erroneous data. In this paper, we survey logic locking approaches and discuss locking quality in hiding expected behavior and in resisting to attacks.

In recent years, FinFET-based Static Random Access Memories (SRAMs) have become a viable solution to provide the storage of big data volume in Systems-on-Chip (SoCs) as well as to assure high performance deep-scaled devices. As consequence, FinFET-based SRAMs are an extremely viable solution to guarantee the high-performance requirements of deep-scaled devices. However, FinFET-based SRAMs can also be affected by resistive defects that may lead to dynamic faults, which are considered one of the most important causes of manufacturing test escape in deep-submicron technologies. Hence, this paper proposes to evaluate the impact of temperature on the dynamic faulty behaviour of 20 nm FinFET-based SRAM cells affected by weak resistive defects. In more details, the critical resistances and the number of consecutive operations necessary to sensitize faults at the logic level are investigated. Additionally, the concept of Dynamic Behaviour Window (DBW) is defined. Results showed that temperature plays a major part in the sensitization of dynamic faults. Thus, the occurrence of dynamic faults has been mapped combining temperature as well as defect size, and the DBW has been defined considering resistive defects. The proposed evaluation helps to understand the behaviour of dynamic faults in memory cells even better and therefore can be used to improve the test procedures for deep-scaled FinFET memory devices. The proposed analysis has been performed using HSPICE simulations adopting a 20 nm Predictive Technology Model (PTM) of multi-gate transistors based on bulk FinFET.