Based on the advantages of higher output efficiency, higher utilization, higher production, lower cost, no requirement for advanced process, higher device density, improved electrical performance and enhanced thermal management, there are many foreign manufacturers and domestic manufacturers all have developed the fan out panel level packaging (FOPLP) technology in the past ten years. The related technologies including die first & face down for FOPLP technology, die first & face up for FOPLP technology and RDL first for FOPLP technology have been developed. The challenges including die shift, panel warpage, RDL process capability, relayed equipment, and market share also need to be considered for a long time along with the developing of FOPLP technology. During the whole process of FOPLP packaging, organic materials including epoxy molding compound (EMC), dry film, photosensitive polyimide (PSPI) and photoresist (PR) were applied to guarantee the performance of packaged chips.

The shrinking of the size of the advanced technological nodes brings up new challenges to the semiconductor manufacturing community. The optical proximity correction (OPC) is invented to reduce the errors of the lithographic process. The conventional OPC techniques rely on the empirical models and optimization methods of iterative type. Both the accuracy and computing speed of the existing OPC techniques need to be improved to fulfill the stringent requirement of the research and design for latest technological nodes. The emergence of machine learning technologies inspires novel OPC algorithms. More accurate forward simulation of the lithographic process and single turn optimization methods are enabled by the machine learning based OPC techniques. We discuss the latest progress made by the OPC community in the process simulation and optimization based on machine learning techniques.

The electronic properties and transport properties of MoTe2/SnS2 heterostructure Tunneling FETs are investigated by the density functional theory coupled with non-equilibrium Green’s function method. Two dimensional (2D) monolayer MoTe2 and SnS2 are combined to a vertical van der Waals heterojunction. A small staggered band gap is formed in the overlap region, while larger gaps remain in the underlap source and drain regions of monolayer MoTe2 and SnS2 respectively. Such a type-II heterojunction is favorable for tunneling FET. Furthermore, we suggest short stack length and large gate-to-drain overlap to enhance the on-state current suppress the leakage current respectively. The numerical results show that at a low drain to source voltage Vds = 0.05V, On/Off current ratio can reach 108 and the On-state currents is over 20 μA/μm for n-type devices. Our results present that van der Waals heterostructure TFETs can be potential candidate as next generation ultra-steep subthreshold and low-power electronic applications.

During the past decade, significant progress has been achieved in the application of material modeling to aid technology development in semiconductor manufacturing companies such as Intel. In this paper, we review examples of applications involving a complex set of material modeling tools and methodologies and share our perspective of the future of the area. Examples are given illustrating the landscape of useful physical models and approaches along with commentary addressing tool relevance and simulation efficiency issues. While the scope of this paper precludes providing in-depth details, references to more focused publications are shared. Finally, we outline how to approach constructing a general infrastructure for supporting TCAD material modeling applications.

This paper presents a TCAD-based methodology to enable Design-Technology Co-Optimization (DTCO) of advanced semiconductor memories. After reviewing the DTCO approach to semiconductor devices scaling, we introduce a multi-stage simulation flow to study the device-to-circuit performance of advanced memory technologies in presence of statistical and process variability. We present a DRAM example to highlight the DTCO enablement for both memory and periphery. Our analysis demonstrates how the evaluation of different possible technology improvements and design combinations can be carried out to maximize the benefits of continuous technology scaling for a given set of manufacturing equipment.

With the continuous scaling in conventional CMOS technologies, the planar MOSFET device is limited by the severe short-channel-effect (SCE), Multi-gate FETs (MuG-FET) such as FinFETs and Nanowire, Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node. The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates. Due to the relatively more mature process and rich learning of the device physics, the FinFET is still extended to 5 nm technology node. In this paper, we proposed a 5 nm FINFET device, which is based on typical 5 nm logic design rules. To achieve the challenging device performance target, which is around 15% speed gain or 25% power reduction against the 7 nm device, we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability. Based on our preferred device architecture, we provide our brief process flow, key dimensions, and simulated device DC/AC performance, like Vt, Idsat, SS, DIBL and parasitic parameters. As a part of the final evaluation, RO simulation result has been checked, which demonstrates that the Performance Per Area (PPA) is close to industry reference 5 nm performance.

5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet (EUV) lithography on a large scale. We have done a simulation study for typical 5 nm logic design rule patterns. In a 5 nm logic photo process, the most appropriate layers for the EUV lithography are the cut layers, metal layers, and via layers. Generally speaking, critical structures in a lithography process are semi-dense patterns, also known as the “forbidden pitch” patterns, the array edge structures, tip-to-tip structures, tip-to-line structures (under 2D design rules), the minimum area structures, the bi-lines, tri-lines, …, etc. Compared to that from the 193 nm immersion process, the behaviors for the above structures are different. For example, in the 193 nm immersion process, the minimum area is about 2~3 times that of minimum pixel squared, while in EUV photolithographic process, the minimum achievable area is found to be significantly larger. In the simulation, we have kept aware of the stochastics impact due to drastically reduced number of photons absorbed compared to the DUV process, the criteria used for various structures of image contrast are tightened. For example, in 193 nm immersion lithography, we have usually set the minimum Exposure Latitude (EL) for the poly layer, the metal layer, and tip-to-tip pattern, respectively, at 18%, 13%, and 10%. However, in EUV lithography, reasonable targets for the minima are, respectively, >18%, 18%, and 13%. We have also studied the aberration and shadowing impact to the above design rule structures. We will present the results of our work and our explanations.

Sub-resolution assist features have been widely recognized in lithography patterning. In general, the insertion of assist features in optically adjacent space around main designed features, will change the aerial image intensity profiles of corresponding main features. Optimizing assist feature placement lets the main feature obtain optimal or better image contrast, better imaging resolution and depth of focus (DOF). Recent EUV lithography development, however, imposes strict budget of edge placement error and process window control causing assist features to become more and more complex. In this domain, 1D assisting feature can no longer meet such tight requirements, and 2D assisting features have become necessary in the semiconductor industry. In this paper, the process window and edge placement error evaluations of different 2D assist feature types are reviewed, along with their associated run time and memory consumption. Various types of 2D assist features are evaluated, including 45-degree disconnected assist features, 45-degree connected assisting features, Manhattan only assist feature arrays, and so on. To generate the assist features, the model-based assisting feature rule table is first generated using the optical model as the reference. The rule table is then split into different rule sets by considering the dimensions and types of assisting features. Finally, the CD variations across process window are evaluated as the success criteria of each assist feature rule sets. In addition, an inverse lithography technology (ILT) based approach is proposed to generate the optimized rule table, as ILT is well known to have considerable benefits in finding the best pattern solutions to improve process window, 2D CD control, and resolution in the low K1 lithography regime. At the end of this paper, the summary discusses how the assisting feature placement can be further optimized using leading-edge technologies like machine learning.

The Atomic Layer Deposition process (ALD) is widely used in FinFET, 3D-NAND and other important technologies because of its self-limiting signature and low growth temperature. In recent years, the development of computer enables chances for ALD process simulation in order to improve the process R&D efficiency. In this paper, steady state theory and vacuum pump theory are implemented to develop the growth rate algorithm of atomic layer deposition. The dynamic evolution of the deposition profile is realized based on cellular automata method, and fits the relationship between temperature and growth rate in HfO2 deposition. The model accuracy and simulation results are verified with high reliability. Based on the simulation results of this model, the influence of different substrate size and environmental dose on growth rate of pore structure is studied and analyzed. In the case of deep hole, high depth-to-width ratio hole, or when the gas entry time is below saturation, the growth rate decreases at the pore bottom. Meanwhile, the simulation considering the angle-of-inclination of the hole’s tapered sidewall indicates that the greater the angle, the better the distribution of flux.

3D NAND technical development and manufacturing face many challenges to scale down their devices, and metrology stands out as much more difficult at each turn. Unlike planar NAND, 3D NAND has a three-dimensional vertical structure with high-aspect ratio. Obviously top-down images is not enough for process control, instead inner structure control becomes much more important than before, e.g. channel hole profiles. Besides, multi-layers, special materials and YMTC unique X-Tacking technology also bring other metrology challenges: high wafer bow, stress induced overlay, opaque film measurement. Technical development can adopt some destructive methodology (TEM, etch-back SEM), while manufacturing can only use non-destructive method. These drive some new metrology development, including X-Ray, mass measure and Mid-IR spectroscopy. As 3D NAND suppliers move to >150 layers devices, the existing metrology tools will be pushed to the limits. Still, the metrology must innovate.