Hermetic wafer-level Cu-Sn solid-liquid interdiffusion (SLID) bonding was investigated to explore the sensitivity of selected process parameters with regard to voiding and possible reduction of strength. Little or no variation was observed in the void density as a result of modifying the plated Sn thickness, the storage time between plating and bonding, the bonding tool pressure, or the thermal budget during bonding. All shear tested samples showed excellent shear strength, with an average value within 110–164 MPa. Some statistically significant differences in shear strength were found due to the variations of the process parameters. However, the differences were too small to be critical for the application. Analysis of fracture surfaces showed that the shear strengths in the lower range corresponded to fracture between the adhesion layer (TiW) and the silicon cap, while shear strengths in the higher range corresponded to fracture in the Cu3Sn formed during the bonding. The results indicate that the investigated bonding process is robust with regard to the studied process parameters.

Nowadays, in many applications, limited space and weight budgets are two important variables that the designer should handle. Many fields such as aerospace or portable electronics require extremely small interconnection solutions, which go behind standard cables and connectors. To overcome this problem, we present the design, fabrication, and testing of an ultra-low-weight spacer for PCB to PCB interconnections. The novelty of this work is that this paper presents an easy and reliable solution capable of creating strong electrical and mechanical bonding at the same time. The extremely limited weight of the spacer (74 mg) and the relatively small dimension (5 mm × 5 mm) make this system a possible solution for applications requiring minimal space and weight.

A 4H-SiC bipolar technology suitable for high-temperature integrated circuits is tested with two interconnect systems based on aluminum and platinum. Successful operation of low-voltage bipolar transistors and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27°C up to 500°C for both the metallization systems. When operated on −15 V supply voltage, aluminum and platinum interconnect OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of aluminum and platinum interconnects was evaluated by performing accelerated electromigration tests at 300°C with current density of about 1 MA/cm2 on contact chains consisting of 10 integrated resistors. Although in both cases the contact chains failed after less than one hour, different failure mechanisms were observed for the two metallization systems: electromigration for the aluminum system and poor step coverage and via filling for the platinum system.

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.

Modern active electronically steered antennas (AESA) operate in different platforms and systems. Inside EADS/CASSIDIAN, the focus on X-band antennas today is on airborne and fighter nose radars, in satellite based SAR antennas (synthetic aperture radar) for earth observation, and ground surveillance and security radars. Active antennas are assembled with hundreds or even thousands of transmit/receive modules. This paper will describe an example of a so-called standardized module solution based on LTCC package technology. State-of-the-art modules are assembled with active components such as MMICs realized in GaAs technology, for example, the low noise amplifier (LNA) and the high power amplifier (HPA), silicon based devices, and passives. Assembly technologies are optimized for high yield series production inside CASSIDIAN MicroWave Factory. New semiconductor technologies, such as GaN (gallium nitride) are enablers for a new transmit/receive module generation. GaN/SiC based MMICs with higher power density compared with GaAs-based devices are technological challenges for innovative thermal management solutions and assembly alternatives. GaN power devices are soldered on modern heat sink materials with high thermal conductivity and matched CTE (between the MMIC and the heat sink). The results of thermal simulations comparing different heat sink materials in combination with soldering techniques will be discussed and an optimized solution will be shown. Another type of transmit/receive module technology based on RF-PCB and packaged MMICs will be discussed. Future applications of ground-based security radars, active antenna products with a one-dimensional array, and the need for cost-effective solutions seem to be a good fit for SMD-based products. Different packages, for example, QFN (quad flat pack no lead) and ceramic based (HTCC), mainly for power devices will be shown and compared.

The performance of electronics in harsh environments is often affected by a combination of environmental factors. Qualification tests on such electronics are normally carried out by separate environmental tests such as temperature storage, temperature cycling and vibration tests. This approach may miss the effects of combined parameters, where for example, there may be degradation in a vibration environment that may be accelerated by temperature related effects on material properties. This paper presents results from a study of the combined effects of temperature and vibration on wire bonded interconnections that are used in the production of high temperature electronic components. The study is focused on the testing of electronic components under the combination of temperature exposure up to 250°C and vibration loading with a frequency range between 500 Hz and 2,000 Hz and acceleration up to 20 Grms. The study covers aspects of wire bond connections and their failure mechanisms, where the effect of wire loop height and length under separate and combined vibration and temperature tests has been investigated. The study has also assessed the effect on packaged Silicon on Insulator (SOI) devices assembled into ceramic packages under representative combined temperature and vibration profiles. The work has shown that the combined effect of temperature and vibration has increased the susceptibility of wire bond interconnections to vibration-induced failures.

Printable conductors with high conductivity are critical for low-cost printed electronics. From the view of printability, conductivity, and electrical stability, an ideal candidate would be a metal such as gold or silver derived from solution-deposited precursor compositions. We have been exploring the use of silver nanoparticles as the conductor precursor for printed electronics. This paper reviews our research in the development of alkylamine-stabilized silver nanoparticles that can be sintered at a low temperature (∼120°C) for high conductivity (>10,000 S/cm). Silver nanoparticle ink formulations based on these silver nanoparticles exhibit surface-energy independent printability, which enables the fabrication of high-performance top-contact transistor devices, and self-assembly characteristic when printed on hydrophilic substrates, which allows for large-area, defect-free source/drain arrays to be printed with a narrow and uniform channel length.

Increased heat generation in semiconductor devices for demanding applications leads to the investigation of highly efficient cooling solutions. Effective options for thermal management include passing of cooling liquid through the microchannel heat sink and using highly conductive materials. In the author's previous work, experimental and computational analyses were performed on LTCC substrates using embedded silver vias and silver columns forming microchannels. This novel technique of embedding silver vias along with forced convection using a coolant resulted in higher heat transfer rates. The present work investigates the design optimization of this cooling system (microheat exchanger) using systems optimization theory. A new multiobjective optimization problem was formulated for the heat transfer in the LTCC model using the log mean temperature difference (LMTD) method of heat exchangers. The goal is to maximize the total heat transferred and to minimize the coolant pumping power. Structural and thermal design variables are considered to meet the manufacturability and energy requirements. Pressure loss and volume of the silver metal are used as constraints. A hybrid optimization technique using sequential quadratic programming (SQP) and branch and bound method of integer programming has been developed to solve the microheat exchanger problem. The optimal design is presented and sensitivity analysis results are discussed.

When packaging electronics to protect from the effects of water vapor, it is essential to be able to predict how moisture will permeate the enclosure. In the context of short term medical implants, for instance, packages made of a permeable material such as a polymer may be acceptable, provided calculations and tests show that low internal relative humidity (RH) is guaranteed for the required device lifetime. A method is presented to evaluate the permeation of water vapor into a package with desiccant, and tests are described to evaluate the validity of the model experimentally. Achievable lifetimes for PEEK packages with silica gel are investigated.

Thermal underfills are crucial to support integration density scaling of future integrated circuit packages. Therefore, a sequential process using hierarchical self-assembly of microparticles and nanoparticles is proposed to achieve percolating thermal underfills with enhanced particle contacts. The three main process steps are assembly of filler particles by centrifugation, formation of nanoparticle necks by capillary bridging, and backfilling of the porous structure with an unfilled capillary adhesive. Numerical simulations predicting trajectories and distributions of micron-sized particles dispensed into a rotating disk are presented. The trajectories exhibit a strong dependence on particle size; thus, in the case of polydisperse filler particles, nonuniform particle beds may result. An efficient centrifugal disk design with spiral-like guiding structures is experimentally validated. Defect-free, percolating particle beds in confined space with fill fractions of 46 vol.% to 66 vol.%, that is, close to the theoretical limit, are also presented. The self-assembly of nanoparticles, forming enhanced thermal contacts between the percolating filler particles, is discussed. Two consecutive evaporation patterns during the capillary bridging process were identified: (1) dendritic network growth, and (2) collapse of capillary bridges. The concave neck topology could only be achieved at temperatures below the boiling point. An optimal evaporation temperature of 60°C with respect to in-plane uniformity and neck shape was identified. Existing thermal gradients normal to the cavity surface resulted in strongly asymmetric neck formation in the cavity. Hence, uniform heating in an oven is the preferred method to initiate evaporation. Two types of bimodal dielectric necks are demonstrated. Polystyrene acts as the adhesive between thermally conductive alumina particles to form mechanically stable dielectric necks after an annealing step at 140°C. Interstitial and core-shell necks are presented. Finally, a benchmark study was performed to compare the effective thermal conductivity of the percolating thermal underfill with and without necks with state-of-the-art capillary underfills. A close to fivefold improvement could be obtained for diamond filler particles with silver necks (3.8 W/m·K).