Abstract To overcome the limitations of Orthogonal Frequency Division Multiplexing (OFDM) under mobility conditions, several alternative waveforms have been proposed, each offering distinct benefits and limitations. A promising approach for future wireless communications, including 6G and beyond, is to unify these waveforms to accommodate diverse operating conditions and user requirements. However, processing multiple computationally intensive waveforms on a traditional Application-Specific Integrated Circuit (ASIC) is impractical due to its fixed design. In contrast, Coarse-Grained Reconfigurable Array (CGRA), a typical class of reconfigurable architectures, provides greater flexibility and efficiency, making it a more feasible alternative for such demanding workloads. In this paper, we propose a unified modulator framework that integrates five different waveforms onto a single CGRA platform. This approach demonstrates the run-time reconfiguration capabilities of CGRAs, enabling seamless switching between waveforms to support a unified modulation model. To optimize execution, this work explores overlapping computational and memory-access patterns for the target waveforms, enhancing performance and efficiency. For evaluation, the proposed design is synthesized on a Stratix-IV FPGA device and compared against existing implementations that focus on fixed, single-waveform architectures. The unified modulator implementation achieves an operating frequency of 170.0 MHz, a throughput of 10.88 GOPS and a dynamic power dissipation of 528 mW. Additionally, the scalability of the proposed approach is evaluated across various input sizes (8 $$\times$$ 4, 8 $$\times$$ 8, 16 $$\times$$ 16), demonstrating its flexibility with promising results.

This paper presents a scalable hardware and software architecture for a Passive Surveillance Sonar (PSS) system, enabling real-time processing of high-bandwidth data using multicore processors and high-speed telemetry interfaces. Larger arrays, required to detect quieter submarines in noisy environments, increase data loads; a novel scheme is proposed for efficient transfer between the digitizer and processor. The beamformer, the most computationally demanding component, is analyzed in its time-domain delay-and-sum, frequency-domain, and minimum variance distortionless response (MVDR) forms, including variants for different array structures. The architecture is evaluated with cylindrical arrays of up to 7,600 sensors generating 4 Gbps of data. The parallel and pipelined design achieves real-time performance and scalability. Experiments demonstrate the formation of 450 panoramic beams, detecting and tracking multiple targets with $$3^\circ$$ bearing accuracy.

Abstract The medium-density parity-check (MDPC) code-based cryptosystem remains a finalist of the post-quantum cryptography standard. The row-layered Min-Sum decoding achieves an efficient trade-off between performance and complexity. Parallel row-layered MDPC decoders are designed in previous studies by enforcing constraints on the parity-check matrix. The preliminary work introduces two schemes to reduce the latency without increasing the constraints on the parity-check matrix, which may bring security concerns. The first scheme simultaneously processes multiple identity blocks in the parity-check matrix, and the second processes a larger block of variable width each time. However, their speedup is limited by data access conflicts. In this paper, optimizations are proposed for the computation scheduling of each scheme to further reduce the latency. Out-of-order processing of identity blocks is proposed for the first scheme to reduce memory access conflicts, enabling more simultaneous processing of multiple blocks. For the second scheme, out-of-order processing of block segments is explored to update more messages simultaneously without causing conflicts in layered decoding. Efficient hardware architectures have also been designed for both of the proposed scheduling optimizations. For an example code, the two proposed optimizations achieve 35% and 9%, respectively, speedup over the best prior designs with negligible area overhead. The out-of-order processing is more effective on the first design.