Abstract Taking inspiration from the brain on how to create energy efficient and low latency
neuromorphic systems has the potential to create new opportunities with AI across many
domains. Firstly, it creates a possibility to mitigate problems with too large digital signal
processing costs in various technologies. Secondly, it also enables the use of AI and
machine learning algorithms where it is currently impossible due to energy constraints.
Recently, neuromorphic technology has been introduced to radio communication and radar
applications. In this work, we highlight advantages of applying energy efficient, low latency
and often lightweight neuromorphic computing for radar and radio signal processing. We
perform a comprehensive review of the main current works on neuromorphic technology
for radar applications, focusing on frequency-modulated continuous-wave and synthetic
aperture radar. Additionally, we cover radio frequency signal classification for both radar
and radio signals. Our ambition is to facilitate research on neuromorphic computing for
radar and radio systems, as well as help bringing researchers from these fields together.

Abstract Neuromorphic vision made significant progress in recent years, thanks to the natural match between spiking neural networks and event data in terms of biological inspiration, energy savings, latency and memory use for dynamic visual data processing. However, optimising its energy requirements still remains a challenge within the community, especially for embedded applications. One solution may reside in preprocessing events to optimise data quantity thus lowering the energy cost on neuromorphic hardware, proportional to the number of synaptic operations. To this end, we extend an end-to-end neuromorphic line detection mechanism to introduce line-based event data preprocessing. Our results demonstrate on three benchmark event-based datasets that preprocessing leads to an advantageous trade-off between energy consumption and classification performance. Depending on the line-based preprocessing strategy and the complexity of the classification task, we show that one can maintain or increase the classification accuracy while significantly reducing the theoretical energy consumption. Our approach systematically leads to a significant improvement of the neuromorphic classification efficiency, thus laying the groundwork towards a more frugal neuromorphic computer vision thanks to event preprocessing.

Abstract Symbol decoding in multiple-input multiple-output (MIMO) wireless communication systems requires the deployment of fast, energy-efficient computing hardware deployable at the edge. The brute-force and exact maximum likelihood (ML) decoder, solved on conventional classical digital hardware to decode MIMO symbols, has exponential time complexity. Approximate classical solvers implemented on the same hardware have polynomial time complexity at the best. In this article, we design an alternative ring-oscillator-based coupled oscillator array (also known as oscillatory neural network (ONN)) to act as an oscillator Ising machine (OIM) and heuristically solve the ML-based MIMO detection problem. Complementary metal oxide semiconductor (CMOS) technology is used to design the ring oscillators, and ferroelectric field effect transistor (FeFET) technology is chosen as the non-volatile memory (NVM) coupling element (X) between the oscillators in this CMOS + X OIM design. For this purpose, we experimentally report high linear range of conductance variation (1 µS to 60 µS) with programming voltage pulses in a HfO 2 -based FeFET device fabricated at 28 nm high-K/ metal gate (HKMG) CMOS technology node. We incorporate the conductance modulation characteristic in SPICE simulation of the ring oscillators connected in an all-to-all fashion through a crossbar array of these FeFET devices. We show that the above range of conductance variation of FeFET is suitable to obtain best OIM performance, thereby making FeFET a suitable NVM device for this application. Our SPICE simulations show that there is no significant performance drop for symbol detection up to MIMO array sizes of 90 transmitting and 90 receiving antennas. Our simulations, combined with analytical treatment using Kuramoto model of oscillators, predict that this designed classical analog OIM, if implemented experimentally, will offer logarithmic scaling of computation time with MIMO size, thereby offering huge improvement (in terms of computation speed) over exact and approximate classical solvers run on conventional digital hardware.

Abstract Analog in-memory computing (AIMC) offers a promising solution to the von Neumann bottleneck. However, deploying transformer models on AIMC remains challenging due to their inherent need for flexibility and adaptability across diverse tasks. For the benefits of AIMC to be fully realized, weights of static vector-matrix multiplications must be mapped and programmed to analog devices in a weight-stationary manner. This poses two challenges for adapting a base network to hardware and downstream tasks: (i) conventional analog hardware-aware (AHWA) training requires retraining the entire model, and (ii) reprogramming analog devices is both time- and energy-intensive. To address these issues, we propose AHWA low-rank adaptation (AHWA-LoRA) training, a novel approach for efficiently adapting transformers to AIMC hardware. AHWA-LoRA training keeps the analog weights fixed as meta-weights and introduces lightweight external LoRA modules for both hardware and task adaptation. We validate AHWA-LoRA training on SQuAD v1.1 and the GLUE benchmark, demonstrate its scalability to larger models, and show its effectiveness in instruction tuning and reinforcement learning. We further evaluate a practical deployment scenario that balances AIMC tile latency with digital LoRA processing using optimized pipeline strategies, with RISC-V-based programmable multi-core accelerators. This hybrid architecture achieves efficient transformer inference with only a 4% per-layer overhead compared to a fully AIMC implementation.

Abstract The fields of machine learning and artificial intelligence drive researchers to explore energy-efficient, brain-inspired new hardware. Reservoir computing encompasses recurrent neural networks for sequential data processing and matches the performance of other recurrent networks with less training and lower costs. However, traditional software-based neural network (NN) require high energy due to computational demands and massive data transfer needs. A hybrid photonic–electronic reservoir computing (RC) system overcomes this challenge with neuromorphic photonic integrated circuits or NeuroPICs, combining passive photonic reservoirs with electronic readout layers. Here, we introduce a hybrid photonic–electronic RC solution for modulation format identification in C-band telecommunication network monitoring. The NeuroPIC is built on a silicon-on-insulator platform featuring a 4-port reservoir architecture. We discuss the NeuroPIC design, fabrication, experimental performance, and compare it with simulations. The system incorporates nonlinearity through a simple digital readout and achieves close to 100% accuracy in identifying quadrature amplitude modulation formats transmitted over 20 km of optical fiber at a 32 Gbaud symbol rate. The NeuroPIC performance is robust against fabrication imperfections like waveguide propagation loss, phase randomization, and delay line length variations. Experimental results surpassed simulations, attributed to enhanced ‘richness’ of signal interference in the physical system. By integrating an energy-efficient photonic analog processing with electronic readout, this hybrid system reduces the dependence on fully digital NNs, offering a pathway for high-speed temporal data processing in various applications. While system-level energy metrics require further exploration, our work highlights the potential of hybrid approaches to balance performance, fabrication tolerance, and computational efficiency in real-world applications.

Abstract Working memory serves as a crucial building block in cognitive systems due to its fundamental role in information processing and decision-making. Acting as a temporary storage and manipulation mechanism, working memory enables individuals to actively hold and manipulate relevant information essential for ongoing tasks. This cognitive function is pivotal for various complex processes, including problem-solving, language comprehension, and decision-making. This paper introduces a novel working memory model designed as a spiking recurrent neural network of excitatory and inhibitory neurons. The proposed model incorporates biological mechanisms that allows attractors to be active phasically, thereby reducing the energy budget associated with maintaining attractor states. The core innovation of the model lies in its ability to leverage phasic attractors for state-dependent computation in a probabilistic manner. By modulating the activity of attractors via synaptic delays, the model demonstrates context-sensitive information processing. The results showcase the efficiency gains achieved by the proposed phasic attractor mechanism and highlight the model’s capacity for flexible and adaptive information processing.

Abstract The Vision Zero Program’s purpose is to reduce traffic-related fatalities and serious injuries while promoting equitable, safe, and healthy mobility for all. Ultimately, the challenge is to detect pedestrians during the day and especially at night to implement safety measures. The current study introduces an award-winning low-power solution employing neuromorphic visual sensing and hybrid neuro-statistical processing developed by the Technische Hochschule Nürnberg team for the TinyML Vision Zero San Jose Competition. The solution proposes a novel neuromorphic edge fusion of spiking neural networks and event-based expectation maximization for the detection and tracking of pedestrians and bicyclists. We provide a deployment-ready evaluation of the detection performance along with robustness, energy footprint, and weatherization while emphasizing the advantages of the neuro-statistical edge solution and its city-level scaling capabilities.

Abstract In an era characterized by the rapid growth of data processing, developing new and efficient information processing technologies has become a priority. We address this by proposing a novel type of neuromorphic technology we call Fused-MemBrain. Our proposal is inspired by Golgi’s theory modeling the brain as a syncytial continuum, in contrast to Cajal’s theory of neurons and synapses being discrete elements. While Cajal’s theory has long been the dominant and experimentally validated view of the nervous system, recent discoveries showed that a species of marine invertebrate (ctenophore Mnemiopsis leidyi) may be better described by Golgi’s theory. The core idea is to develop hardware that functions analogously to a syncytial network, exploiting self-assembled memristive systems and combining them with complementary metal oxide semiconductor (CMOS) technologies, interfacing with the silicon back-end-of-line. In this way, a memristive self-assembled material can cheaply and efficiently replace the synaptic connections between CMOS neuron implementations in neuromorphic hardware, enhancing the capability of massively parallel computation. The fusion of CMOS circuits with a memristive ‘plexus’ allows information transfer without requiring engineered synapses, which typically consume significant area. As the first step toward this ambitious goal, we present a simulation of a memristive network interfaced with spiking neural networks. Additionally, we describe the potential benefits of such a system, along with key technical aspects it should incorporate.