Abstract Word line (WL) to memory hole (MH) shorts are a common defect in 3D NAND Flash Memory devices. The introduction of multi-tier 3D NAND technologies brings with it unique defect modes, and in this paper, we studied a specific subset of WL-MH shorts unique to multi-tier 3D NAND. These defects specifically affect the WLs beneath the joint (where the upper and lower tier connect). Physical analysis of the defects determined that misalignment between the upper memory hole (UMH) and lower memory hole (LMH) is the root cause of these shorts.

Abstract This paper discusses the proper sample preparation through parallel lapping of a Metal-Insulator-Metal Capacitor (MIMCAP) within an integrated circuit (IC) device. By utilizing a proper nanoprobe Electron Beam Induced Resistive Change (EBIRCH) technique, a distinct hotspot can be created at the nanoscale, enabling precise defect localization. This technique significantly improves the accuracy of Focused Ion Beam (FIB) cross-sectioning, ensuring a more accurate cut at the defect site. Compared to the traditional OBIRCH method, which often produces large hotspots and may result in offsets, the proposed approach offers a more reliable and precise solution for defect identification for Metal-Insulator-Metal Capacitors (MIMCAP).

Abstract With the tremendous growth of design complexity coupled with the diminishing time-to-market duration, the chances of bugs escaping into the first fabricated silicon is getting higher. Design-for-debug capability is then crucial to identify the root cause of the bugs to get fixes intercepted timely. However, when the debug capability failed to gain access, all the internal signal observation will be blocked thus poses debug challenges. This paper presents a debug methodology performed on a silicon issue with more than 10% yield loss on chipset where the hardware-based authentication failed and blocked all Design-For-X capability. This debug is performed on tester with optical/physical probing capability that pinpointed the issue to damaged fuse array and voltage level monitoring (VM) which causes the fuse sensing to fail. The root cause of this issue together with the design fix incorporated in the next silicon stepping are also discussed in this paper.

Abstract Silicon photonics is increasingly important for advancing optical communication networks. The reliability testing of silicon photonics is a critical issue. This study demonstrates damp heat and temperature cycling reliability tests for silicon photonics, followed by failure analysis (FA).

Abstract In recent decades, automation has not played a significant role in the field of failure analysis. The process of searching for a defect in a single field return sample involves a multitude of manual analysis steps, applying different methods and FA techniques. However, regarding mass data FA and constructional analysis, as is practiced in high-volume foundry fabs or in the context of a substantial number of RMA samples, automation can result in significant resource savings and improved tool utilization. The recent advancements in FIB-SEM instruments, when employed in conjunction with programmable tool kits, have resulted in the acquisition of reliable, high-resolution, automated slice and view cross-section data sets. The generation of a 3D model out of the data sets facilitates a comprehensive evaluation of the defects by enabling an assessment from multiple directions. This paper explores the subsequent step in the process of automatic defect detection. We demonstrate a variety of approaches to automatically detecting defects using conventional image processing and artificial intelligence based segmentation.

Abstract This paper presents a novel system utilizing argon ion milling technology with multiple detectors to delayer a semiconductor sample, achieving nanometer flatness over a millimeter scale. The Chipmill creates an artificial-free surface for further imaging and testing of device properties, which will shorten the time required for new chip development and accelerate the failure analysis process.

Abstract We present a fast, scalable methodology for evaluating Hot Electron Induced Punch-through (HEIP) degradation in advanced memory devices, combining early-time predictive modeling with layout-informed process analysis. Conventional HEIP testing requires 19 hours per word-line with limited spatial coverage, posing significant time and efficiency challenges. By leveraging 1-hour degradation data, we achieved accurate long-term degradation estimation (R² = 0.943) across 200 production wafers, enabling expanded spatial testing from two to 16 memory blocks per die. Blocks located near the chip center consistently showed minimal degradation, and layout inspection identified the absence of Redistribution Layer (RDL) coverage in these blocks, prompting a SHOT-level Process Window Qualification (PWQ) with selective RDL via removal. Follow-up testing showed only marginal global degradation suppression, indicating limited structural influence in this case. These results illustrate how the proposed approach can efficiently identify layout-related degradation factors and can be broadly applied to support reliable, data-driven process optimization in semiconductor manufacturing.

Abstract Laser voltage probing of decap fill cells in standard-cell logic is explored for on-die measurement of dynamic voltage droop and other applications. These FinFET based decaps offer unprecedented access to the local power grid for making non-contact noise measurements because they are widespread in modern CMOS logic ICs. Compared to logic cells, their waveform interpretation is simplified because they are non-switching and less impacted by signal crosstalk. Examples of this novel use of decaps will be provided for 5 nm and 3 nm test vehicles. Possible methods for voltage calibration will be discussed and some examples provided. Other potential applications of decap laser voltage probing and imaging will also be discussed.

Abstract Heterogeneous technology has evolved significantly from its origins in multi-chip modules to advanced packaging techniques that integrated separately manufactured components into a unified system. This paradigm, often described as “More than Moore,” allows for the continued scaling of performance beyond traditional transistor miniaturization. While integration of functionally diverse components, often fabricated at different process notes, into a single package offers system-level advantages, it introduces new challenges for both electrical and physical failure analysis. This study investigates the mechanical effects of die relaxation during deconstruction by systematically removing individual chiplets and tracking curvature changes in the SoC die. The goal is to develop a reliable strategy for sample preparation that minimizes stress induced damage during failure analysis. Curvature evolution was explored across a range of 2.5D and 3D heterogeneous devices featuring various chiplet configurations and the presence or absence of stiffener rings.

Abstract Transmission electron microscopy (TEM) and related characterization techniques are widely used to inspect semiconductor devices. Conventional TEM (CTEM) and scanning TEM (STEM) methods mostly keep the incident electron beam at a fixed angle, aligned with the optical axis of the electron microscope. While effective in many scenarios, this invariance could limit the potential for more complex applications. We investigate a technique that allows us to acquire multidimensional data from a series of beam tilt angles. The acquired data can be further processed to provide more information and to reduce the possible errors associated with single data sets. In this paper, we demonstrate the advantages of this technique through several semiconductor use cases. These benefits include reducing unwanted background information in electric field mapping on a SiC film, enhancing strain mapping quality on a Si-SiGe multilayer structure and improving grain mapping on a 3D-NAND device. This beam-tilt technique can be executed via an automated script once the experimental conditions are optimized, paving the way for large-volume investigation through automated TEM.