Abstract In complementary FET (CFET) architectures, the vertically stacked device configuration inherently limits heat dissipation paths, leading to severe self-heating effects (SHE), particularly in the upper device. This work presents an electro-thermal and reliability analysis of CFETs employing a dualsubstrate architecture, which provides an additional thermal conduction path to mitigate SHE. The proposed structure is quantitatively compared with nanosheet FETs (NS-FETs), monolithic CFETs (mCFETs), and sequential CFETs (sCFETs) under identical operating conditions using precisely calibrated 3D TCAD simulations. Electro-thermal simulation results show that, compared to the NS-FET, the dual-substrate CFET with a 30-nm top silicon layer reduces the maximum temperature rise (∆T MAX ) and thermal resistance (R TH ) from 60.3% and 76.3% in the conventional sCFET to 12.6% and 26.1%, respectively. To identify the optimal substrate thickness, a figure of merit (FoM), defined as the product of propagation delay and maximum temperature (T MAX ), is introduced. The FoM reaches a minimum at a top substrate thickness of 30 nm, indicating the optimal performancethermal trade-off. Furthermore, device reliability is quantitatively evaluated in terms of hot-carrier injection (HCI) and bias temperature instability (BTI) lifetime models, showing 4.7× and 10.5× improvements, respectively, for the proposed CFET with a 30-nm additional substrate compared to the conventional sCFET. These results demonstrate that the proposed structure effectively alleviates SHE in CFETs and provides improved long-term device reliability for advanced logic applications.
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