ABSTRACT Semiconductor and Semi equipment industries expect to see a strong upturn in the next few years, with advanced packaging technologies a significant beneficiary of the markets strength. 5G, AI, Edge Computing, Persistent Memory, Integrated Power Management, and the transition to sub 5nm silicon technology are all driving the need for innovative packaging solutions. These solutions integrate silicon produced with disparate process nodes and deliver maximum performance at optimal cost. Heterogeneous Integration, utilizing a multitude of interconnect methodologies (from Fan-out to Silicon Interposer, to Chiplet), addresses this challenge but requires unique solutions for efficient, cost effective die placement. High speed, high precision multi-die placement, directly and efficiently extracted from a range of different sized wafers, is critical to enable cost effective assembly. This paper looks at the challenges and potential approaches for efficient and cost effective solutions.

ABSTRACT Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm 2 body size, 18×15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a -40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.

ABSTRACT With growing demand for advanced computing systems and as personal handheld devices become more powerful, front-end manufacturers are required to reduce the physical footprint of and at the same time integrate more functionality into their chips. More I/O channels are packed into smaller areas than ever before in modern packages. The competing demands of increasing throughput and reducing costs makes the interconnection of these packages increasingly challenging. New methods to produce these high-density interconnections are required to meet these challenges. Chips are placed and connected both horizontally and vertically in 2.5D and 3D packaging. This created inherent topographical challenges for producing the interconnections. The industry’s drive for cost reduction is building momentum toward more efficient and cost effective methods for creating the multi-layer high density interconnects. There are inherent topographical challenges associated with the growth of 2.5D and 3D packaging where chips are placed and interconnected horizontally and vertically. One critical area of interest is the formation of the passivation layer that enables connections between layers. Polyimides must be applied in a uniform layer to ensure that the inter-layer connections can properly be formed. Effectiveness of different film deposition methods is measured in terms of formation of uniform and void-free films to ensure intended mechanical and electrical integrity of the material is not compromised. Film deposition method can potentially influence not only film density but also polymer chain configuration that control key properties directly linked to the reliability of the material. While polarity of functional groups dictates moisture uptake, polymer chain configuration can control moisture permeability through the deposited film and its ability to act as corrosion barrier. We have previously reported creation of high-density vias printed in a dielectric film deposited by a revolutionary technique in the form of a novel nozzle-less ultrasonic spray technology. [1] This paper presents impact of such unique deposition method on key film properties like density and moisture permeability along with supporting reliability data under high temperature storage (HTS) and unbiased-HAST conditions. Other key performance parameters like filling and planarization over complex topography of an advanced dielectric material will be compared and analyzed for this approach against other liquid film deposition techniques.

ABSTRACT Recently we have developed novel polyimide adhesive sheet materials (PI sheet) which have advantages such as planarization, via-filling, low shrinkage (low stress) during curing and easy fabrication of multi-layer and cavity structures compared to spin-coating polyimide materials. The PI sheets are expected to be used in wafer level package (WLP) applications such as 5G telecommunication systems (5G) and Micro Electro Mechanical Systems (MEMS). To meet 5G and MEMS requirements, we recently have developed novel low-dielectric loss (low Df) and high mechanical properties PI sheets with good adhesion to Cu and polyimide layers on a substrate. We have achieved Df values of 0.003 and 0.007 at 20GHz for non-photosensitive (NP) PI sheet and photo-sensitive (PS) PI sheet, respectively. The use of low Df PI sheet as a redistribution layer can help realize low transmission loss due to low Df value itself and also to low conductor loss due to good adhesion to the smooth copper surface of the wiring.

ABSTRACT As demand for ever more powerful personal handheld devices and advanced computing systems continues to grow, front-end manufacturers have pushed Moore’s Law to the limit and integrated more functionality into their chips while at the same time reducing their physical footprint. Modern chips now contain more I/O channels in smaller areas than ever before. The interconnection of these devices has become more challenging along with competing demands to reduce costs and increase throughput. New methods are required to meet these challenges. There are inherent topographical challenges associated with the growth of 2.5D and 3D packaging where chips are placed and interconnected horizontally and vertically. The industry’s drive for cost reduction is building momentum toward more efficient and cost effective methods for creating the multi-layer high density interconnects. One critical area of interest is the formation of the passivation layer that enables connections between layers. Polyimides must be applied in a uniform layer to ensure that the inter-layer connections can properly be formed. This paper demonstrates the feasibility of a revolutionary technique in the form of nozzle-less ultrasonic spray technology in conjunction with a next generation advanced packaging lithographic system for the creation of high-density vias. Performance parameters including polyimide thickness uniformity, and CDU will be compared and analyzed for this approach against other liquid film application methods. Results from the examination of the efficacy, cost reduction potential of this novel method for high-volume manufacturing will be presented.

ABSTRACT In mobile application, to integrate the required functions in the limited area is one of the key points of the success of the products. The industries have studied the way of integration method by adopting system on chip or system in package approach. With the conventional approach using laminate substrate, there had been the limit of integration due to its limited pattern capability and larger keep out zone for underfill. It’s known that fan-out package is one of the effective solutions to make the compact system. One of the most important factors is to achieve fine joint pitch to make the system within Package on Package format. In this study, the system integration by using advanced packaging technology like fan-out PLP will be provided. One of wearable devices had been selected to see the effect of integration. In conventional approach, the devices had been placed on main PCB, respectively. To make the area compact, some of PKG types were selected and compared. Finally, we had found the most effective package format for fine form factor.

ABSTRACT The new 5G wireless standard brings several new challenges for many applications, especially for the wafer level chip scale packaging (WLCSP) technology. WLCSP has been a very successful technology for handheld and portable products. To make the right decisions in the early stages of probe card design for the mmWave frequencies wafer test, the electromagnetic (EM) simulation of the probe card performance is inevitable. Critical is an understanding of the dependencies and relationships between the many interacting probe card parts such as probe head, PCB, and coaxial connectors. This paper describes the challenges in wafer testing for 5G applications and presents the author’s experience in the implementation of spring probe cards for 5G mmWave frequencies. This paper presents a spring probe card for 5G technology as a low-cost alternative RF wafer test solution and examines 3D EM computer model simulation results.

ABSTRACT With the drive towards adding more functionality on a system and the era of artificial intelligence and IoT in play, the semiconductor industry has responded by moving away from the Moore’s law approach of shrinking the chip and instead focusing on 3D integration of dies and/or packages. While by itself this poses significant challenges in the manufacturing and testing of these new architectures, there is also a need to address the issues this creates for the design flow itself. The key difference in design flow is the increasing number of iterations, not only of designs, but also the combination of designs. One die may be used across multiple packages or PCBs. This necessitates the need to create flows which are cognizant of variations. Added to this is the complexity of having to tackle new architectures like fan out wafer-level packaging or 3D ICs. The classical methodology of passing the design information from the between chip/package and package/PCB teams will be much too restrictive, costly and potentially the key to faster time-to-market product. This paper explores the solution to this the complex system connectivity optimization challenge and further demonstrates a way to track and verify connection changes throughout the design process.

ABSTRACT We study the role of via size and aspect ratio in defect-free electroplating of through silicon vias in 3DICs. Using a level-set curvature enhanced adsorbate coverage model, we simulate the electroplating of vias of various sizes and aspect ratio by varying the overpotential and the initial copper concentration. We find that as the via size and aspect ratio increases, the filling fraction reduces and voids are formed in the vias. Increasing overpotential also reduces the filling fraction. We show that in all these cases, increasing the initial copper concentration can result in increased filling of the vias of higher aspect ratios.

ABSTRACT Laser release materials have become an important topic in the semiconductor industry for wafer-level packaging (WLP) due to its many advantages over other temporary bond and debond (TB/DB) methods, including mechanical and thermal slide. These methods enable higher wafer throughput, subject the device to less physical stress, and allow access to new applications where strong adhesion between material interfaces are necessary, such as fan-out wafer level packaging (FOWLP) to prevent delamination and spontaneous debond due to high stress during the process. However, with the significant benefits laser release materials offer, there are still challenges that affect the current generation of materials. The majority of these challenges are caused by low energy absorbance of current materials, which can result in increased carbon residue, potential device damage from extended laser penetration, high laser energy for debond, long cleaning times (due to thicker coatings and high carbon residue), and the possibility that materials may not effectively debond using commercially available tools such as 308-nm, 343-nm and 355-nm laser wavelengths. The research within this study addresses all of the aforementioned challenges and includes the developmental results of a next generation of laser release materials showing significant advancements to overcome challenges. Next-generation materials have greatly improved performance with increased absorbance of laser energy at 308-nm, 343-nm, and 355-nm wavelengths. This allows materials to debond with lower energy, protect the device from laser energy, produce almost no carbon residue upon ablation, and greatly reduce cleaning time because these materials offer all of this utilizing a thinner coat. This next generation of laser release materials brings an additional benefit of strong open-face solvent resistance without requiring long, high-temperature bakes or compromising the decomposition temperature of the material.