Memory Address Research Articles (Page 5)

Achieving energy efficiency is of paramount importance in facilitating the deployment of artificial intelligence (AI) applications, particularly for edge devices. The computational complexity and memory requirement of AI workloads have made energy efficiency in circuits the primary design constraint, prompting a need for architectural reconsideration. However, operations in Convolutional Neural Networks (CNN) relying on matrix multiplication offer opportunities for algorithm-level optimization. The dynamic power consumption in CMOS technology exhibits a direct correlation with the switching activities (SA) associated with transitions of data bits from one cycle to the next. Minimizing SA constitutes an effective approach to curbing power consumption, resulting in prolonged battery life. This work introduces a cross-layer end-to-end optimization technique, which involves a one-time sorting of pre-trained model parameters to reduce switching activity during matrix multiplication or convolution operations while eliminating the indexing overhead during inference. While upto 40% reduction in switching activities through sorting has been achieved, the actual saving in dynamic power achievable for the input stationary systolic array is approximately 10% in total power consumption and around 15% in switching power. The proposed method has been validated using various pre-trained networks, including GoogeLeNet, MobileNet, AlexNet, and SqueezeNet, among others.

Structural damage identification for large-scale structures with uncertainties consumes numerous computational time and memory. The substructuring method is a model order reduction method, which is helpful to alleviate the computational burden. This paper proposes a statistical damage identification method using substructure-based stochastic finite element model updating to rapidly identify the damage of each element. First, the reduced order model of global structure is derived by retaining a few substructural modes as the reduction basis, where the inertial and elastic effects of discarded modes are considered. Next, the mean and standard deviation of identified structural parameters are rapidly solved by performing first-order perturbation analysis on the finite element model updating-based damage identification function of the reduced order model. Finally, the damage probability of each element is obtained using the mean and deviation of identified structural parameters before and after damage. A numerical one-bay plane frame and a numerical highway bridge are applied to verify the accuracy and efficiency of the proposed method.

The emergence of large-scale quantum computing presents an imminent threat to contemporary public-key cryptosystems, with quantum algorithms such as Shor’s algorithm capable of efficiently breaking RSA and elliptic curve cryptography (ECC). This vulnerability has catalyzed accelerated standardization efforts for post-quantum cryptography (PQC) by the U.S. National Institute of Standards and Technology (NIST) and global security stakeholders. While theoretical security analysis of these quantum-resistant algorithms has advanced considerably, comprehensive real-world performance benchmarks spanning diverse computing environments—from high-performance cloud infrastructure to severely resource-constrained IoT devices—remain insufficient for informed deployment planning. This paper presents the most extensive cross-platform empirical evaluation to date of NIST-selected PQC algorithms, including CRYSTALS-Kyber and NTRU for key encapsulation mechanisms (KEMs), alongside BIKE as a code-based alternative, and CRYSTALS-Dilithium and Falcon for digital signatures. Our systematic benchmarking framework measures computational latency, memory utilization, key sizes, and protocol overhead across multiple security levels (NIST Levels 1, 3, and 5) in three distinct hardware environments and various network conditions. Results demonstrate that contemporary server architectures can implement these algorithms with negligible performance impact (<5% additional latency), making immediate adoption feasible for cloud services. In contrast, resource-constrained devices experience more significant overhead, with computational demands varying by up to 12× between algorithms at equivalent security levels, highlighting the importance of algorithm selection for edge deployments. Beyond standalone algorithm performance, we analyze integration challenges within existing security protocols, revealing that naive implementation of PQC in TLS 1.3 can increase handshake size by up to 7× compared to classical approaches. To address this, we propose and evaluate three optimization strategies that reduce bandwidth requirements by 40–60% without compromising security guarantees. Our investigation further encompasses memory-constrained implementation techniques, side-channel resistance measures, and hybrid classical-quantum approaches for transitional deployments. Based on these comprehensive findings, we present a risk-based migration framework and algorithm selection guidelines tailored to specific use cases, including financial transactions, secure firmware updates, vehicle-to-infrastructure communications, and IoT fleet management. This practical roadmap enables organizations to strategically prioritize systems for quantum-resistant upgrades based on data sensitivity, resource constraints, and technical feasibility. Our results conclusively demonstrate that PQC is deployment-ready for most applications, provided that implementations are carefully optimized for the specific performance characteristics and security requirements of target environments. We also identify several remaining research challenges for the community, including further optimization for ultra-constrained devices, standardization of hybrid schemes, and hardware acceleration opportunities.

IntroductionPremature Ventricular Contractions (PVCs) can be warning signs for serious cardiac conditions, and early detection is essential for preventing complications. The use of deep learning models in electrocardiogram (ECG) analysis has aided more accurate and efficient PVC identification. These models automatically extract and analyze complex signal features, providing valuable clinical decision-making support. Here, we conducted a study focused on the practical applications of is technology.MethodsWe first used the MIT-BIH arrhythmia database and a sparse low-rank algorithm to denoise ECG signals. We then transformed the one-dimensional time-series signals into two-dimensional images using Markov Transition Fields (MTFs), considering state transition probabilities and spatial location information to comprehensively capture signal features. Finally, we used the BiFormer classification model, which employs a Bi-level Routing Attention (BRA) mechanism to construct region-level affinity graphs, to retain only the regions highly relevant to our query. This approach filtered out redundant information, and optimized both computational efficiency and memory usage.ResultsOur algorithm achieved a detection accuracy of 99.45%, outperforming other commonly-used PVC detection algorithms.DiscussionBy integrating MTF and BiFormer, we effectively detected PVCs, facilitating an increased convergence between medicine and deep learning technology. We hope our model can help contribute to more accurate computational support for PVC diagnosis and treatment.

The Internet of Things (IoT) has begun transforming our digital space, in which everyday objects are interconnected and capable of communicating with each other. This transformation not only simplifies our lives but also creates unprecedented opportunities and enhances efficiency in areas such as smart homes, healthcare, industrial manufacturing, and urban management. However, as with any technological breakthrough, IoT requires a careful and well-planned implementation. The large-scale and unregulated deployment of IoT devices raises significant security concerns that must be mitigated.At the core of IoT devices lies the ability to autonomously collect, process, and transmit information independently of human intervention. While this autonomy is the primary innovation, it also introduces numerous security vulnerabilities. For instance, IoT devices often operate on private and public networks, increasinf the attack surface for malicious actors capable of compromising data confidentiality and integrity. However, security is not the sole concern. The reliability and availability of the critical functions these devices provide are equally crucial. From thermostats and smartwatches to autonomous vehicles and urban infrastructure, compromised IoT devices can cause anything from minor inconveniences to catastrophic failures affecting millions.IoT devices typically have limited computational power and memory. These constraints often render the implementation of traditional security measures, such as complex encryption algorithms, impractical. Given these limitations and the explosive growth in the number of IoT devices, the potential for unauthorized interference with systems also increases. According to Cybersecurity Ventures, the number of IoT devices worldwide is expected to reach 25.1 billion by 2025. Each device represents a potential entry point for attackers. This widespread proliferation creates a vast, often poorly secured, network of interconnected devices susceptible to exploitation by malicious actors for data theft, DDoS attacks, and other cyber threats.The infrastructure surrounding IoT devices can be divided into four levels: perception (node capture, node impersonation, replay attack, timing attack, sleep deprivation attack), network (eavesdropping, DoS/DDoS attacks, Man-in-the-Middle attacks), data processing (resource exhaustion, exploits), and application (exploits). Therefore, key security challenges in IoT include unauthorized access to devices and data, communication interception, data manipulation, and depletion of system and device resources.The purpose of this article is to describe a comprehensive proposed solution for securing IoT systems. There is an urgent need for scalable and reliable solutions. Our approach considers the unique characteristics of IoT ecosystems, particularly their diversity, limited computational resources, and the physical nature of the devices.

Currently, data mining based on machine learning plays a key role in decision support in various industries. An important practical problem of machine learning is the implementation of object classification in real time, which can be achieved by parallelizing data processing algorithms both for input data and for decision function data. To improve the efficiency of parallelizing machine learning methods, a unified decision function model has been developed. The Relevance of this research is to present a unified decision function model in the framework of machine learning algorithms and functions for its parallelization both in terms of input data and decision function data.The essence of the presented approach is that the features of the operation of metric methods of machine learning are analyzed, independent data for processing are presented using different categories of the analyzed property, developed decision function model describes the object features for input data and decision function data using standardized elements and including functions for their parallel processing based on group parallelization of objects. The proposed approach is based on the use of methods for analyzing algorithms and computational complexity, mathematical statistics and the methodology of designing parallel algorithms. Experiments have shown that parallelization of the proposed decision function model for the potential function method allows increasing the classification efficiency for one object using additional computing resources, and for a group of objects within the limits of the computer's memory size or planning horizon.The novelty of the proposed approach is that the model differs from existing ones in a method of formalizing objects and their features using unified elements for training and classification objects and has a structure and functions oriented towards its parallel processing by pattern recognition methods based on decision functions within the framework of group parallelization of objects. Theoretical significance: the model is unified and can be used to parallelize other pattern recognition methods that can be described by similar parameters, architecture, and classification features. The practical significance of the proposed approach is that the model allows decomposing the pattern classification problem into separate subtasks of finding regularities between input data and decision function data.

Abstract We review space–time isogeometric analysis and in particular present and extend the unconditionally stable space–time isogeometric method introduced in Fraschini et al. (Comput Math Appl 169:205–222, 2024) for the linear acoustic wave equation to multi-patch spatial domains. This formulation incorporates a stabilization strategy that enhances numerical robustness by penalizing high-order derivatives within the variational framework. Additionally, we present a solver that exploits the Kronecker structure of the problem, eliminating the need to assemble global space–time matrices, and reduces computational overhead and memory usage. A numerical experiment is proposed, that confirms the method’s stability, accuracy, and computational efficiency, highlighting its effectiveness for large-scale wave propagation problems on complex geometries.

The von Neumann bottleneck is a major challenge in the development of energy-efficient processors capable of handling high-workload computations. Computing-in-memory (CiM) technique offers a promising solution to overcome the memory wall restrictions that limit performance. By embedding processing units directly into memory, CiM can mitigate issues of latency and energy consumption during memory access. In this study, we implemented a dual-port design method for a 10-Transistor (10T) SRAM bit-cell to perform Binarized Multiply-Accumulate operation using 45nm CMOS process technology. We use several functional block designs, including isolated read and write paths, to design the 1Kb CiM architecture using the Cadence Virtuoso EDA tool. The proposed 10T SRAM-CiM design supports fully parallel computing, allowing it to perform 32 Binarized MAC operations simultaneously. The design achieves a maximum operating frequency of 100MHz, a throughput of 204.8 GOPS and energy efficiency of 443.15 TOPS/W.

Fuzzy Association Rule Mining (FARM) extends traditional ARM by evaluating and pruning rules based on interestingness measures to identify relevant patterns for various applications. The focus of this paper is to explore the application of FARM techniques demonstrating its algorithmic implementation in a meteorological dataset. Three major algorithms known as fuzzy Apriori, FTDA (Fuzzy Transaction Data-Mining Algorithm) and CFARM Composite Fuzzy Association Rule Mining) are experimented and analyzed. The experiment uses a real meteorological dataset spanning twenty years consisting some important attributes of weather such as rainfall, temperature, relative humidity, wind speed and bright sunshine hours of the North Bank Plain Zone (NBPZ) of the Brahmaputra River in Assam, India. The collected dataset is pre-processed into a transaction dataset and converted into a fuzzy dataset using membership functions. The three FARM algorithms are subsequently employed to uncover associations among various attributes within the fuzzy meteorological dataset. This study analyzes experimental results from three algorithms, focusing on factors like rule generation, computation time, and memory consumption. While Fuzzy Apriori provides comprehensive rule generation, it comes at the cost of higher computation time and memory usage. FTDA and CFARM, on the other hand, offer more efficient and significant rule generation, making them more suitable for large-scale, complex data analysis. The findings of this paper can contribute to the development of resilient and efficient data mining frameworks, enhancing the decision-making process for stakeholders in the meteorological domain. Thus, the paper introduces a new method for analyzing meteorological data using Fuzzy Association Rule Mining (FARM) techniques.

SRAM-based computing-in-memory (CIM) is an efficient technology for computing neural networks where matrix operations are dominated. However, leveraging sparsity in CIM presents challenges due to the crossbar architecture, which complicates the avoidance of zero element calculations. Previous CIM designs have demonstrated that sparsity can improve energy efficiency, but these approaches often lead to non-negligible accuracy loss or substantial hardware overhead. To address this challenge, we propose a hybrid N:M CIM (HNM-CIM), an algorithm-architecture co-design framework for accelerating Transformers. At the algorithm level, we propose a hybrid N:M pruning (HNMP), a method that combines structured and unstructured sparsity. This approach maintains regularity while preserving the random distributions of sparsity, thereby enhancing model sparsity with negligible accuracy loss and ensuring CIM compatibility. At the hardware level, we introduce a hybrid N:M sparse digital CIM (HNM-CIM) to support HNMP, which can accelerate Transformers with hybrid N:M sparsity patterns. Experimental results show that HNMP can reduce Transformer models by about 3.1× on model size with negligible accuracy loss. Compared with state-of-the-art references, HNM-CIM yields about 2.46× speed up and 1.43× area savings.

Joint sonar-communication (SonarCom) systems offer interesting and promising perspectives for target detection in military or civilian applications. Compared to the traditional sonar systems, orthogonal frequency division multiplexing (OFDM) SonarCom system suffers from frequency offset. The fluctuation due to array uncertainty and acoustic propagation characteristics lead to random phase errors, which heavily impair the estimation accuracy. To deal with this drawback, we present a compressed sensing-based range-angle estimation algorithm when phase errors are present for OFDM SonarCom systems. In order to overcome multitarget interference, cyclic prefix (CP)-based OFDM technique is applied. Exploiting the structure of the CP-OFDM signal model, the redundant dictionary and minimization problem are defined. The coupling information of sparse data are considered as a global metric to minimize the effect of phase errors and recover super-resolution range-angle estimation. Regardless the presence of random phase errors and strong noise, the approach returns high-quality estimates of range and angle. Moreover, a low complexity solution algorithm is developed to improve the computational complexity and memory requirements. The performance assessment underlines that the proposed approach can be a viable means to solve the joint range and angle estimation problem.

Page replacement algorithms play a crucial role in enhancing the performance issue brought on by variations in processor speeds and memory by effectively removing pages from computer memory to improve overall efficiency. The majority of these algorithms can address the page replacement problems, but their implementation is challenging. This paper introduces a new efficient page replacement algorithm, i.e., enhanced least-replacement (E-LRU) based on two introduced features used to select the victim page. By incorporating elements of traditional algorithms such as first in first out (FIFO) and least recently used (LRU), E-LRU presents itself as a new approach with potential benefits for memory management. This study evaluates the effectiveness of E-LRU in reducing power consumption by reducing cache faults and compares its performance to existing algorithms in various settings. The results provide insight into the advantages and disadvantages of E-LRU and essential perspectives on its potential benefits for contemporary memory management algorithms. Furthermore, the study puts E-LRU into the perspective of evolving algorithms and provides directions for future investigation and improvement in the ever-changing field of memory management. The study proved that E-LRU works better than FIFO and LRU algorithms.

The ongoing global energy crisis has heightened the demand for low-power electronic devices, driving interest in neuromorphic computing inspired by the parallel processing of human brains and energy efficiency. Reconfigurable memristors, which integrate both volatile and non-volatile behaviors within a single unit, offer a powerful solution for in-memory computing, addressing the von Neumann bottleneck that limits conventional computing architectures. These versatile devices combine the high density, low power consumption, and adaptability of memristors, positioning them as superior alternatives to traditional complementary metal-oxide-semiconductor (CMOS) technology for emulating brain-like functions. Despite their potential, studies on reconfigurable memristors remain sparse and are often limited to specific materials such as Mott insulators without fully addressing their unique reconfigurability. This review specifically focuses on reconfigurable memristors, examining their dual-mode operation, diverse physical mechanisms, structural designs, material properties, switching behaviors, and neuromorphic applications. It highlights the recent advancements in low-power-consumption solutions within memristor-based neural networks and critically evaluates the challenges in deploying reconfigurable memristors as standalone devices or within artificial neural systems. The review provides in-depth technical insights and quantitative benchmarks to guide the future development and implementation of reconfigurable memristors in low-power neuromorphic computing.

The effect of the recording layer thickness (t) on the quasi-static switching characteristics in the double MgO/CoFeB interfaces perpendicular magnetic tunnel junctions with the [Co/Pt]n-based synthetic antiferromagnetic structures has been investigated. It is apparent that the switching current drops rapidly either with slightly increasing the bottom CoFeB thickness (tCoFeB ≥ 1.15 nm) or inserted Ta thickness (tTa ≥ 0.3 nm), or with marginally decreasing the upper CoFeB thickness (tCoFeB ≤ 0.75 nm), even acquiring a maximum reduction of 41.8%. The tuning mechanism of the write energy dissipation at a specific pulse width can be attributed to two parts. One is an intrinsic leverage of the effective ferromagnetic volume, spontaneous magnetization, and magnetic anisotropy field in the recording layers with a view to their dead layer. The secondary contributors may be closely related to the discrepancy between the resistance-area products of the perpendicular magnetic tunnel junction devices with the six different stack designs. Our results are instructive to the future development of practical ultralow-power chips in binary memory and logical computation fields.

Multi-agent pathfinding (MAPF) holds significant utility within autonomous systems, however, the calculation and memory space required for multi-agent path finding (MAPF) grows exponentially as the number of agents increases. This often results in some MAPF instances being unsolvable under limited computational resources and memory space, thereby limiting the application of MAPF in complex scenarios. Hence, we propose a decomposition approach for MAPF instances, which breaks down instances involving a large number of agents into multiple isolated subproblems involving fewer agents. Moreover, we present a framework to enable general MAPF algorithms to solve each subproblem independently and merge their solutions into one conflict-free final solution, and avoid loss of solvability as much as possible. Unlike existing works that propose isolated methods aimed at reducing the time cost of MAPF, our method is applicable to all MAPF methods. In our results, we apply decomposition to multiple state-of-the-art MAPF methods using a classic MAPF benchmark\footnote{https://movingai.com/benchmarks/mapf.html}. The decomposition of MAPF instances is completed on average within 1s, and its application to seven MAPF methods reduces the memory usage or time cost significantly, particularly for serial methods. Based on massive experiments, we speculate the possibilty about loss of solvability caused by our method is $<$ 1\%. To facilitate further research within the community, we have made the source code of the proposed algorithm publicly available\footnote{https://github.com/JoeYao-bit/LayeredMAPF/tree/minimize\_dependence}.

Neuromorphic computing, inspired by the biological brain’s efficiency in processing information, has emerged as a revolutionary paradigm for next-generation edge artificial intelligence (AI). This research presents a comprehensive bio-inspired neuromorphic framework that leverages spiking neural networks (SNNs), memristor-based synaptic architectures, and event-driven processing to achieve unprecedented energy efficiency and real-time adaptability in edge computing environments. The proposed system introduces a dynamic spike encoding mechanism that optimizes neuronal activation based on input relevance, coupled with adaptive synaptic pruning to minimize redundant computations. Additionally, the integration of spike-timing-dependent plasticity (STDP) enables continuous self-learning, making the system highly effective for dynamic edge applications such as autonomous navigation, real-time healthcare monitoring, and industrial IoT anomaly detection. Experimental validation demonstrates that the proposed neuromorphic framework achieves a 60% reduction in power consumption, a 3× improvement in processing speed, and a 45% enhancement in model adaptability compared to conventional deep learning models deployed on edge platforms. Hardware efficiency is further amplified through memristor-based in-memory computing, eliminating the energy overhead associated with von Neumann architectures. Real-world evaluations across multiple edge scenarios—including neuromorphic vision processing with event-based cameras—confirm significant improvements in latency, robustness, and scalability. The findings underscore the transformative potential of neuromorphic computing in enabling sustainable, low-power AI for next-generation edge devices. Future research directions include hybrid neuromorphic-deep learning integration and quantum-inspired architectures to further enhance performance and scalability in ultra-low-power edge AI applications.

Supplemental Material for True and False Recognition in MINERVA2: Integrating Fuzzy-Trace Theory and Computational Memory Modeling

Memristive in-memory computing has demonstrated potential for solving matrix equations in scientific computing. However, the inherent inaccuracies of analog mechanisms create challenges in achieving high-precision solutions while maintaining low-energy consumption. This study introduces a memristive matrix equation solver that considerably accelerates solutions by performing mathematical iterations directly within an analog domain. Our approach facilitates rapid approximate solutions with a scalable circuit topology and expedites the high-precision refinement process by substantially reducing the digital-to-analog conversion overhead. We experimentally validated this methodology using a heterogeneous computing system. We performed simulations of multiple scientific problems on these circuits, including solving the diffusion equation and modeling equilibration in silicon P-N junctions. Notably, our memristive solver, combined with digital refinement, achieved software-equivalent precision (with an error of 10-12). Compared to conventional digital processing units, this approach offered a 128-fold improvement in solution speed and a 160-fold reduction in energy consumption. This work establishes a foundation for future scientific computing using imprecise analog devices.

Drone-based synthetic aperture radar (SAR) systems have increasingly gained attention due to their potential for rapid surveillance in localized areas. This paper presents a novel approach to SAR processing for subsurface target detection from a lightweight drone platform. The limited processing capacity and memory resources of small SAR platforms demand efficient recovery performance for high-resolution imaging. Compressed sensing (CS) algorithms are widely used to mitigate data storage requirements, yet they often suffer from challenges related to computational burden and detection errors. CS theory exploits signal sparsity and the incoherence of sensing matrices to reconstruct target information from reduced data measurements. Although random sensing matrices are commonly employed to ensure the independence of measured data, they incur high computational cost and memory resources. While deterministic sensing matrices provide fast data recovery, they suffer from increased internal interference, leading to degraded performance in noisy environments. This paper proposes a novel hybrid sensing matrix and recovery algorithm for efficient target detection in small drone-based SAR platforms. After establishing the principles of signal sampling and recovery, SAR imaging simulations are conducted to evaluate the performance of the proposed method with respect to data compression, processing speed, and recovery accuracy. For verification, a custom-built drone SAR platform is utilized to recover subsurface targets obscured by high-clutter backgrounds. Experimental results demonstrate the effective recovery of buried target images, highlighting the potential of the proposed method for practical applications in high-clutter environments.

ABSTRACTIn this paper, a stress‐relaxed driver system applied to compute‐in‐memory (CIM) is proposed for programming, reading and erasing of the CIM chip. The driver system utilizes a hierarchical regulation method to achieve accurate row and column selectivity, reducing the area overhead of the peripheral driver system for the CIM array. In order to suppress the voltage fluctuation of the power supply and ground caused by direct path currents, power‐delay efficient positive and negative voltage level shifters are proposed. The proposed level shifters allows transistors used in the driver system to switch voltages at the safe operating limit. The driver system based on 1024 2048 floating gate devices is implemented using a 65‐nm CMOS process. The driver system converts a 1.8‐V voltage‐domain input signal to a high‐voltage‐domain output voltage, which meets the requirements of operating transmissions from −10 to 9 V. The simulation results show that the maximum voltage stress in the driver system is less than 12 V, achieving a reduction of 21.9% compared to the previous study. Simultaneous switching of 256 word‐lines can be achieved across the temperature range of −40°C to 125°C with a 2‐pF capacitive load. The driver system can support the switching of the program, erase, and read modes. In the read mode, the delay remains less than 13 ns for the gate voltage of floating gate devices ranging from 3 to 7 V. We conducted the comparative analysis and simulations of the proposed level shifters to elucidate pertinent design trade‐offs. The comparison results show that the proposed level shifters exhibit significant advantages in peak current and power consumption compared with the topologies of various level shifters and have the lowest power‐delay product.