Memory Address Research Articles (Page 7)

Efficient time-domain speech separation using short encoded sequence network

The High-Luminosity Large Hadron Collider (HL-LHC) will significantly increase the number of simultaneous proton-proton interactions per bunch crossing, making efficient track reconstruction increasingly challenging. This study explores the Adaptive Hough Transform (AHT) as an alternative approach to track finding, optimizing the balance between computational efficiency and memory usage. AHT refines parameter space dynamically, reducing the need for a fixed-resolution grid. A stack-based implementation improves performance, making it suitable for accelerator hardware. Optimized precision settings for transverse momentum and azimuthal angle were determined, ensuring high tracking efficiency while minimizing the number of candidate solutions. Additional filtering techniques were introduced to further reduce computational complexity, including line order change counting, peak finding, and data partitioning into overlapping wedges for high pile-up events. These optimizations decreased the average number of solutions per track from 9.8 to 1.8 in single muon events while maintaining over 99% efficiency. For high pile-up (µ 200), AHT, combined with filtering, reduced the number of candidates nearly tenfold, albeit with a slight efficiency drop from 99.1% to 93.2%. These results demonstrate AHT’s viability for real-time tracking applications in HL-LHC environments, offering a robust solution for future upgrades.

Ferroelectric tunnel junctions (FTJs) and ferroelectric diodes (FDs) have been considered as promising artificial synaptic devices for constructing brain-inspired neuromorphic computing systems. However, their functionalities and applications are limited due to their strong dependence on the ferroelectric layer thickness and the thickness optimization is labour-intensive and time-consuming. Here, we demonstrate high-performance electronic synapses based on a high-throughput ferroelectric BaTiO3 (BTO) thin film. Two-terminal ferroelectric memristors are fabricated on a thickness-gradient BTO film with thickness ranging from 1 to 30 unit cells (UC), and intrinsic ferroelectricity is revealed in regions with thickness >5 UC. Notably, three typical resistive switching behaviors of resistor, FTJ, and FD occur sequentially with increasing BTO thickness, allowing these three basic electronic components to be integrated. High-performance FTJ synapses with adaptive conductance compensation from resistor and FD components are proposed based on an on-chip integration configuration. This approach improves the accuracy of handwritten digit recognition using artificial neural networks (ANNs) from 91.3% to 95.7%. Despite Gaussian noise interference, the ANN based on this adaptive compensation approach remains extremely fault-tolerant, and is expected to meet the increasing demands of contemporary electronic devices, particularly in the fields of memory, logic processing, and neuromorphic computing.

Nanoscale optical functionalities show promise for unconventional computing, including neuromorphic and quantum information processing. Resistive switching devices with optical readability have drawn significant research interest for high-density non-volatile memory and unconventional computing. We proposed a multiwavelength nanophotonic circuit consisting of resistive switches based on Ag-SiO2-ITO on a silicon rib structure, with the capability to electrically remove any wavelength channel(s) at will. The device featured a four-layered structure with a SiO2 region positioned between an Ag top electrode and an ITO bottom electrode on p-Si, confining the hybrid plasmonic mode within the SiO2 region. The application of an external voltage caused the formation/rupture of conductive filaments in the SiO2 layer, affecting optical absorption through hybrid mode interactions. Experimental results showed a 27 dB extinction ratio for a 10 μm × 500 nm active device operated at ±2 V. Additionally, the circuit achieved multiwavelength functionality using identical sources and 2 × 1 couplers, enhancing reconfigurability. The higher work function of ITO helped in reducing the energy barrier for ion migration, overcoming the intrinsic resistance of the SiO2 layer. This engineered nanophotonic circuit, with its high extinction ratio, excellent retention, low-voltage operation, and rapid switching speed, is suitable for advanced memory devices, high-speed optical communication, neuromorphic and quantum computation, and programmable photonic circuits.

Classic McEliece has gathered attention as a candidate in NIST post-quantum cryptography standardization. However, it suffers from high demands on the decryption algorithm, making it unsuitable for resource-constrained devices. In this paper, we propose a novel implementation method, named giant footprint sharing, that reduces memory size during decryption in Classic McEliece. The decryption algorithm processes a large number of intermediate variables computed from a secret key in memory. The giant footprint sharing identifies the largest variable among them and allocates a memory-sharing structure to store it, thereby reducing the overall memory size regardless of the implementation platform. The giant footprint sharing can also be combined with existing acceleration techniques, such as fast Fourier transformation. We evaluate Classic McEliece with the giant footprint sharing on the Arm Cortex-M33 CPU and show that it reduces memory size by up to 46% without significant degradation in computation time compared with the existing fast-implementation by Chen et al. (at TCHES 2021). Extensive experiments with the giant footprint sharing further reveal that it maintains a constant memory size regardless of the compiler optimization, and it also achieves an optimal balance in the trade-off between memory size and computation time. The giant footprint sharing is remarkable for any scheme, that contains a large-scale matrix computation and the life cycle for each variable is limited.

Content addressable memories (CAMs) are special-purpose in-memory computing units that support parallel searches directly in memory. There is growing interest in CAMs for data-intensive applications such as machine learning, data mining, and bioinformatics, which has led to a rapidly growing CAM design space. CAM cells can be implemented exclusively by CMOS or with various non-volatile memory (NVM) devices. In addition to traditional binary and ternary CAMs (BCAMs and TCAMs), analog CAM (ACAM) and multi-bit CAM (MCAM) designs have recently been introduced, which could further improve density, and also support unique in-memory distance functions. Furthermore, aside from the widely-used exact match function, CAM-based approximate match functions, such as threshold match and best match, have been proposed to further extend the utility of CAMs to new application spaces. As the CAM design space is large, evaluating different CAM design options for a given application is both crucial and challenging. This paper presents EvaCAM, a circuit-level modeling and evaluation tool for CAMs. EvaCAM supports TCAM, ACAM, and MCAM designs implemented in either CMOS or NVMs, for both exact and approximate match functions. It also allows for the exploration of different CAM designs under various optimization targets. EvaCAM has been validated against measured data from fabricated chips and detailed SPICE simulations. A comprehensive design space exploration for CAMs is provided to illustrate the impact of various design decisions and to demonstrate the use cases of EvaCAM.

In this article, we present a comprehensive design and benchmarking study of content addressable memory (CAM) at the 7-nm technology node in the context of similarity search applications. We design CAM cells based on static random access memory (SRAM), spin-orbit torque (SOT), and ferroelectric field effect transistor devices and from their layouts extract cell parasitics using state-of-the-art electronic design automation (EDA) tools. These parasitics are used to develop SPICE netlists to model search operations. We use a CAM-based dataset search and a sequential recommendation system (RS) to highlight the application-level performance degradation due to interconnect parasitics. We propose and evaluate two solutions to mitigate interconnect effects.

Large language models (LLMs) have gained a lot of attention and achievements recently because of their significant comprehension and generative abilities. However, the large-scale parameters of LLMs require considerable computational resources in the training and inference process, which restricts their wide application. To overcome this challenge, we propose an efficient mixed precision weight quantization (EMWQ) method for LLMs in this article. Specifically, we introduce a new outlier detection method by analyzing the weight distribution instead of the conventional weight magnitude. Then, we propose a dual-quantization strategy that quantizes both the outlier critical columns and the residual matrices with different precision. Besides, we introduce two effective EMWQ-based application frameworks, the EMWQ-R and EMWQ-O in our study. Comprehensive experiments are conducted on the Penn Treebank (PTB), C4, ARC-Easy datasets, and MMLU benchmark across various tasks. The comparison results demonstrate that the proposed EMWQ achieves state-of-the-art performance in mixed precision quantization and further reduces computational memory cost. Besides, it has higher generalizability compared with conventional methods.

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic random-access memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of random-access memory which is not desired and is considered as a challenge for memory cell.

Now, the technological environments rely on a large number of users and devices interconnected in such a way as to be able to share information and exchange resources. For such reasons, security becomes of prime importance inside these networks. Especially, encryption algorithms widely used in smart metering systems form the very backbone of ensuring security. It is unique according to every single parameter: the level of security achieved, speed, operational complexity, length, and type of key used. A comparison of performance and throughput for the most used encryption algorithms, such as AES-128, AES-192, RC4, Blowfish, and ECDSA, is presented here. Such devices, for instance, smart meters, usually represent very resource-constrained computational capability, memory, and data transfer. For these reasons, the experiments investigate performance impacts of using different encryption algorithms on a smart meter environment in a scaled setup. Experiments were run on a laptop device and then downscaled according to the limitation characteristics of the smart meter target device. As for the scaling, it has been performed concerning key factors: CPU of the smart meter, RAM, and cache memory. Execution times of the encryption and decryption processes were measured, as well as the throughput of messages for various file sizes. Quantitative key results obtained included: RC4 with a throughput of 25.37 Kbytes/sec, whereas AES-128 has 4.87 Kbytes/sec, while in ECDSA-256 the performance is much lower: its verification throughput amounts to 0.0023 Kbytes/sec. The results showed significant variations in performance, speed, and throughput between these algorithms. Even considering small smart devices, the encryption and decryption processes yielded efficient throughputs. These findings underscore the importance of choosing the right encryption algorithm for smart meters, balancing both security requirements and resource limitations to ensure optimal performance.

This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). Our study relies on a temperature-aware macrospin-based Verilog-A compact model for MTJ devices and a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X. When implementing logic operations with the SIMPLY scheme operating at 77 K, the DMTJ-based scheme assures energy savings of about 69%, as compared to its SMTJ-based counterpart operating at 77 K. Overall, our results prove that the SIMPLY scheme at cryogenic conditions is a promising solution for reliable and energy-efficient logic-in-memory (LIM) architectures.

Video coding standards are the key enablers of recent video applications, such as video conferencing, video on demand, and immersive video. The recent standards have become more efficient in compressing such video data with higher quality for the user over the years. However, the computational effort of video encoders has also increased due to the new coding tools and the support of higher video resolutions and frame rates. The design of dedicated hardware accelerators, associated with approximate computing and storage techniques, has been used today to deal with such an increase in the computational effort and memory requirements needed to implement recent video encoders. This survey article reviews state-of-the-art works that propose approximate computing and storage techniques and apply them to video coding systems.

In-memory sensing and computing devices integrate the functionalities of sensors, memory, and processors, offering advantages such as low power consumption, high bandwidth, and zero latency, making them particularly suitable for simulating synaptic behavior in biological neural networks. As the pace of digital transformation accelerates, the demand for efficient information processing technologies is increasing, and in-memory sensing and computing devices show great potential in AI, machine learning, and edge computing. In recent years, with the continuous advancement of infrared detector technology, infrared in-memory sensing and computing devices have also seen new opportunities for development. This article reviews the latest research progress in infrared in-memory sensing and computing devices. It first introduces the working principles and performance metrics of in-memory sensing and computing devices, then discusses in detail transistors and memristor-type devices with infrared band response, and finally looks forward to the development prospects of the field. Through innovation in new semiconductor materials and structures, the development trajectory of infrared in-memory sensing and computing devices has been significantly expanded, providing new impetus for the development of a new generation of information technology.

Phase change memory (PCM) is a scalable, reliable, and robust technology for embedded and stand-alone memory device. PCM has also been extensively demonstrated for analog in-memory computing (IMC), which allows energy-efficient acceleration of AI workloads. High-temperature data retention requirements in PCM devices are met by Ge-rich GeSbTe (GST), which allows to satisfy consumer- and automotive-grade reliability specifications. However, Ge-rich GST suffers from set state drift, which affects the stability of the multilevel cell (MLC), hence the accuracy of IMC. This work presents: 1) a novel multilevel programming algorithm from weak reset state to prevent conductance instabilities; 2) a drift compensation scheme through a differential weight approach, validated on matrix-vector multiplication (MVM) after high-temperature annealing; and 3) a detailed study of the impact of PCM variability and weight quantization on hardware implementation of neural networks.

In Automatic Modulation Classification (AMC), extended signal lengths offer a bounty of information, yet impede the model’s adaptability, introduce more noise interference, extend the training and inference time, and increase memory usage. To bridge the gap between these requirements, we propose a novel AMC framework, designated as the Mamba-based Automatic Modulation Classification (MAMC), which addresses the accuracy and efficiency requirements for long-sequence AMC. Specifically, we introduce the Selective State Space Model (Mamba), which enhances the model’s capabilities in long-term memory and information selection, and reduces computational complexity and spatial overhead. We further design a denoising unit to filter out effective semantic information to improve accuracy. Rigorous experimental evaluations on the publicly available dataset RML2016.10 and TorchSig affirm that MAMC delivers superior recognition accuracy while necessitating minimal computational time and memory occupancy. Codes are available on <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/ZhangYezhuo/MAMC</uri>.

Lane detection based on semantic segmentation can achieve high accuracy, but, in recent years, it does not have a mobile-friendly cost, which is caused by the complex iteration and costly convolutions in convolutional neural networks (CNNs) and state-of-the-art (SOTA) models based on CNNs, such as spatial CNNs (SCNNs). Although the SCNN has shown its capacity to capture the spatial relationships of pixels across rows and columns of an image, the computational cost and memory requirement needed cannot be afforded with mobile lane detection. Inspired by the channel attention and self-attention machine, we propose an integrated coordinate attention (ICA) module to capture the spatial-wise relationships of pixels. Furthermore, due to the lack of enhancement in the channel dimension, we created an efficient network with a channel-enhanced coordinate attention block named CCA, composed of ICA and other channel attention modules, for all-dimension feature enhancement. As a result, by replacing many repeated or iterative convolutions with the attention mechanism, CCA reduces the computational complexity. Thus, our method achieves a balance of accuracy and speed and has better performance on two lane datasets—TuSimple and ILane. At less than a few tenths of the computational cost, our CCA achieves superior accuracy compared to the SCNN. These results show that the low cost and great performance of our design enable the use of the lane detection task in autopilot scenarios.

Heterogeneously integrated hybrid photonic crystal cavities enable strong light–matter interactions with solid state, optically addressable quantum memories. A key challenge to realizing high quality factor (Q) hybrid photonic crystals is the reduced index contrast on the substrate compared to suspended devices in air. This challenge is particularly acute for color centers in diamond because of diamond’s high refractive index, which leads to increased scattering loss into the substrate. Here, we develop a design methodology for hybrid photonic crystals utilizing a detailed understanding of substrate-mediated loss, which incorporates sensitivity to fabrication errors as a critical parameter. Using this methodology, we design robust, high-Q, GaAs-on-diamond photonic crystal cavities, and by optimizing our fabrication procedure, we experimentally realize cavities with Q approaching 30,000 at a resonance wavelength of 955 nm.

In this presentation, I will delve into the exciting realm of monolithic 3D integration, where emerging 2D FETs take center stage, empowering advanced memory, and logic devices. Furthermore, I will also discuss our work on bio-inspired neuromorphic computing. Notably, our recent breakthroughs have culminated in the successful demonstration of wafer-scale 2-tier and 3-tier 3D integration, utilizing MoS2 and WSe2 FETs as the building blocks. These achievements have paved the way for multifunctional circuits that hold immense promise for the future of electronics. Delving deeper into our research, we have harnessed the potential of 2D materials to design solid-state devices with low power consumption mimicking auditory processing in barn owl, collision avoidance in locust, and probabilistic computing in dragonfly. By combining the power of 2D materials with bio-inspired principles, our work lays a solid foundation for the creation of highly compact and functionally diverse integrated circuits in the revolutionary third dimension. The implications of this technology are far-reaching and hold the potential to shape the future of electronics and computing.

We have evaluated the feasibility of performing, with gaseous HCl, a lateral selective etching of high versus low Ge content SiGe layers. Such a know-how might be useful to fabricate, besides Complementary Field Effect Transistors, other types of devices relying on stacked nanosheets and multiple selective etchings such as 3D Resistive or Oxyde Random Access Memories (for In-Memory Computing).To that end, we have grown {20 to 25 nm thick Si / ~ 12-15 nm thick Si0.8Ge0.2 or Si0.75Ge0.25 / ~ 11-14 nm thick Si0.5Ge0.5} multilayers on SOI substrates. After a low temperature capping with SiN, such stacks were patterned into regular arrays of square mesas or lines with a stop on the buried oxide, to laterally have access to the layers of interest. The temperature used, in our 300 mm Reduced Pressure - Chemical Vapor Deposition chamber, to grow such stacks was 550°C. Meanwhile, the in-situ HCl etch temperature was always 500°C. The aim of such low process temperatures was to minimize the thermal budget multilayers were submitted to, in order to minimize elastic relaxation and avoid plastic relaxation while still having reasonable growth and etch rates. The overall compressive strain was indeed high in such stacks given the number, individual thicknesses and Ge concentrations of SiGe layers. Multilayers grown at 550°C, 20 Torr with (i) a SiH2Cl2 + GeH4 chemistry for Si0.5Ge0.5, (ii) a Si2H6 +GeH4 chemistry for Si0.75Ge0.25 or Si0.8Ge0.2 and (iii) pure Si2H6 for Si were in some places defective, with the presence on the surface of islands. Such defects were likely due to Si2H6 mass-flows which were too large, resulting in gas phase nucleation and, in some places, the formation of defects that increased in size as growth happened. We thus proceeded differently. Instead of Si2H6 + GeH4, we have used a SiH4 + GeH4 chemistry for the epitaxy of SiGe 20% or 25% layers. We succeeded in having reasonable SiGe 20% and 25% growth rates at 550°C, 20 Torr, which was not a given with that chemistry. We also showed that a x/(1-x) = 2.81*F(GeH4)/F(SiH4) relationship perfectly accounted for the almost linear increase of the Ge concentration x with the F(GeH4)/F(SiH4) mass-flow ratio. We otherwise reduced the Si2H6 mass-flow and added HCl to minimize gas phase nucleation and suppress the formation of amorphous inclusions in the Si layers. The linear dependency of the 550°C, 20 Torr Si growth rate on the Si2H6 and HCl mass-flows was modelled with the following phenomenological relationship: Si Growth Rate (nm min.-1) = 3260*F(Si2H6)/F(H2) – 1070*F(HCl)/F(H2).We then determined, at 500°C, 600 Torr, the (001) blanket HCl etch rates of SiGe 30% and 40%: 1.37 and 5.28 nm min.-1. Based on such data, we should have the following SiGe 50%, 25% and 20% etch rates: 20.0, 0.70 and 0.36 nm min.-1, respectively. Meanwhile, the pure Si etch rate should be negligible: 0.025 nm min.-1 only. Should we then define theoretical selectivities as being ratios between (i) SiGe 50% and (ii) SiGe 25%, SiGe 20% or pure Si blanket (001) etch rates, we would obtain promising selectivities (29, 56 and 800) when laterally etching of SiGe 50% versus SiGe 25% SiGe 20% and Si.We then switched over to patterned wafers. The lateral selective etching of Si0.5Ge0.5 versus Si0.8Ge0.2 (and Si) was feasible. The following features were highlighted: (i) Si0.5Ge0.5 lateral etch rates along the <110> directions were much smaller than in the [001] direction and (ii) because of micro-loading, lateral etch rates were definitely higher for squares than for lines (0.9 - 1.1 nm min.-1 for lines, to be compared with 1.7 – 2.1 nm min.-1 for squares). Meanwhile, the lateral selective etching of Si0.5Ge0.5 versus Si0.75Ge0.25 was far from being perfect, with much higher Si0.5Ge0.5 etch rates and a significant Si0.75Ge0.25 recessing at tunnel entrances (see Figure 1). Si0.75Ge0.25 floors and ceilings were otherwise far more etched and thus tilted than Si0.8Ge0.2 ones. Inserting very thin Si spacers between Si0.5Ge0.5 cores and Si0.75Ge0.25 claddings partly solved those issues, with no recessing and lesser etchings at the entry points of tunnels, then (see Figure 2). Figure 1

Automatic and accurate tooth segmentation on 3D dental point clouds plays a pivotal role in computer-aided dentistry. Existing Transformer-based methods focus on aggregating local features, but fail to directly model global contexts due to memory limitations and high computational cost. In this paper, we propose a novel Transformer-based 3D tooth segmentation network, called PointRegion, which can process the entire point cloud at a low cost. Following a novel modeling of semantic segmentation that interprets the point cloud as a tessellation of learnable regions, we first design a RegionPartition module to partition the 3D point cloud into a certain number of regions and project these regions as embeddings in an effective way. Then, an offset-attention based RegionEncoder module is applied on all region embeddings to model global context among regions and predict the class logits for each region. Considering the irregularity and disorder of 3D point cloud data, a novel mechanism is proposed to build the point-to-region association to replace traditional convolutional operations. The mechanism, as a medium between points and regions, automatically learns the probabilities that each point belongs to its neighboring regions from the similarity between point and region features, achieving the goal of point-level segmentation. Since the number of regions is far less than the number of points, our proposed PointRegion model can leverage the capability of the global-based Transformer on large-scale point clouds with low computational cost and memory consumption. Finally, extensive experiments demonstrate the effectiveness and superiority of our method on our dental dataset.