multiple scan chain Research Articles (Page 1)

Design for testability (DFT) is introduced to reduce the complexity of testing integrated circuit and help improve fault coverage. However, conventional DFT with additional 2-to-1 multiplexer (MUX) might add an increasing amount of delay and area overhead. Therefore, register transfer level (RTL) scan design is introduced to overcome this problem. This paper aims to present the development of an ASIC with RTL scan design by using multiple scan paths instead of the conventional technique, which is gate-level (GL) scan insertion to insert scan cells. This method inserts multiple scan cells by utilizing the existing multiplexer and operational units in order to reduce area overhead and delay. Besides, multiple scan paths are implemented instead of a single scan chain to reduce the complexity of the testing process, where a single scan chain has long test application times due to the high number of clock cycles for the scan chain process. RTL design is also modified by adding an extra gate for multiple scan chain insertion. The graph is derived in order to analyse the connection between registers such that the multiple scan paths can be determined accordingly. Synopsys tool is used for synthesized, placement and routing and performing automatic test pattern generation while static timing analysis is used to verify the results of the setup slack time for ASIC design. The simulation result shows that multiple scan paths insertion at RTL level has an area overhead and slack time of about 3.79% and 0.44ns less compared to multiple scan paths insertion at GL for a finite impulse response circuit with comparable high fault coverage and small delay. A comparison of the performance metrics such as area, setup slack time, and fault coverage of the multiple scan chain is done between the RTL scan and GL scan.

Scan attacks exploit facilities offered by scan chains to retrieve embedded secret data, in particular, secret keys used by the device for data encryption/decryption in mission mode. This paper presents a scan attack countermeasure based on the encryption of the data written to or read from the scan chains. The secret-key management system already embedded in the device is used to provide appropriate keys for encryption of data flowing on the scan chains. The goal of the proposed solution is to counteract the scan-related security threats while preserving test and diagnosis efficiency provided by conventional design-for-testability techniques, as well as to allow debugging capabilities in mission mode. The proposed solution can deal with both stuck-at and transition-faults test schemes as well as single and multiple scan chain configurations using test data compression schemes. We will show that the proposed scheme provides expected test/diagnostic and debug facilities as classical scan design with marginal impacts on area, test time and design flows, while successfully preventing control and observation of data flowing in the scan chains by unauthorized users.

As test data continues to grow quickly, test cost also increases. For the sake of decreasing the test cost, this article presents a new data dependency compression scheme for large circuit which is based on multiple scan chains. We propose new compression architecture with fixed length for running tests. In results, when the complexity of a VLSI circuit is growing, the number of input pins for testing is very low. Since test data in power aware is not changed frequently, we use a selector to filter the unnecessary status and buffers to hold the back data. We also propose a new algorithm to assign multiple scan chains and an improved linear dependency compute method to find the hidden dependency between scan chains. Experimental results show that the proposed method can reduce both test data volume and shift-in power.

This paper proposes a scan disabling-based BIST-aided scan test (BAST) scheme. In this scheme, a pseudo-random pattern generator(PRPG) generates test vector for each slice in multiple scan chains. Using scan disabling technique, the generated test vector is shifted into the scan chains until it is compatible with its corresponding slice for a deterministic test set with don't care bits. An automatic test equipment (ATE) only needs to store the control signals instead of test data. The proposed scheme that is based on the standard scan and uses any test set with don't care bits is widely applicable and easy to deploy. Its hardware overhead that is a PRPG, phase shifter, MISR and scan disable signal is very low. Theoretical analysis and experimental results show the proposed scheme can achieve higher compression gain compared with previous low cost scheme when care bits are few.

Test technology based on multiple parallel scan chains is widely used for production tests of integrated circuits. Beyond the problem of efficient test data compression, aspects of heat dissipation during testing have become a major matter of concern in recent years. In normal operation modes circuits may work close to their thermal limits. Therefore innovative test technologies and automatic test pattern generators (ATPG) algorithms need to generate test stimuli that utilize circuits more efficiently without causing excessive high thermal stress. For this reason a modified STUMPS architecture together with an optimization strategy is presented which aims at reduced power consumption (80 percent reduction over pure linear feedback shift register solutions) during scan test and high test compaction rates. Both aims could be weighted against each other as required.

Broadcast-based test compression techniques can reduce both test data and test time. However, the success of such methods heavily depends on the percentage of test patterns that can be broadcasted. In this paper, we first conduct a quantitative analysis that shows the simple broadcast architecture that cannot achieve good test time/data compression even under a test set with very high level of don't care bits. A multi-mode-segmented scan test architecture (MSSA) is then presented to solve the problem of low broadcast rate. Three operation modes are supported in this architecture: broadcast, multicast and serial. As a result, improved test data compression is achievable with limited hardware overhead, as serial-mode operations are largely eliminated. An algorithm for the two-way partitions of the scan segments is proposed to construct multicast mode configurations. Finally, we present a layout-aware scan chain ordering method to further improve test compression. The problem of ordering scan cells in multiple scan chains is mapped to a constrained standard cell placement problem in physical synthesis, and the simulated annealing method is used to solve the problem. The routing length of the scan chains are also taken into account in the ordering process.

In this paper, we investigate the problem of assigning scan cells to multiple scan chains based on physical placement. We formulate a new multichain assignment (MA) problem and discuss its complexity and relationship to partitioning and traveling salesman problems. We show that MA is not adequately solved by approaches based on the traveling salesman methods alone and present two new algorithms for MA based on partitioning and stable marriage (SM) problems. We demonstrate that even though partitioning-based methods offer significant improvements compared to previous methods, the SM-based algorithm offers the best results. We compare our algorithms with previous work based on preplacement and greedy assignments in terms of total scan net lengths and maximum load capacitance of scan cells. Experiments with ISCAS89 benchmarks indicate that our algorithms improve the chain lengths 50%-90%, while reducing the maximum load capacitance by 30%-50%.