Processor Types Research Articles (Page 1)

Low levels of product literacy among consumers often cause a mismatch between the specifications of the purchased mobile phone and their actual needs. This problem is common, especially in stores that provide a wide selection of products with technical information that is poorly understood by prospective buyers. Lack of understanding of features such as processor type, camera quality, RAM capacity, and internal memory makes the purchasing process less than optimal. This study aims to improve consumer literacy by developing a mobile phone purchase recommendation system based on the C4.5 algorithm. The method used is a data mining approach with stages of collecting historical consumer purchase data, preprocessing data to eliminate noise, labeling purchase decisions, forming a decision tree model using the C4.5 algorithm, and evaluating model performance using a confusion matrix. The dataset used includes 19 types of mobile phones from a local store with attributes such as processor, main camera, front camera, RAM, internal memory, and price. The method used in this study uses the C4.5 algorithm. The results of the study show that the C4.5 algorithm is able to classify data with satisfactory accuracy and produce a relevant recommendation system. In addition to providing product suggestions, this system also includes a logical explanation of each decision taken, thereby increasing consumer understanding. Thus, this system not only helps the decision-making process, but also acts as an educational medium in increasing consumer literacy regarding mobile phone product specifications that suit their needs and budget.

FRESH: Fault-tolerant Real-time Scheduler for Heterogeneous multiprocessor platforms

On the variance propagation of thermistor-based measurements with a digital temperature controller

Firmware is software embedded in a device and acts as the most fundamental work of a system. Disassembly is a necessary step to understand the operational mechanism or detect the vulnerabilities of the firmware. When disassembling a firmware, it should first obtain the processor type of running environment and the image base of firmware. In general, the processor type can be obtained by tearing down the device or consulting the product manual. However, at present, there is still no automated tool that can be used to obtain the image base of all types of firmware. In this paper, we focus on firmware in ARM and propose an automated method to determine the image base address. Firstly, by studying the storage rule and loading mode of the function address, we can obtain the function offset and the function address loaded by LDR instruction, respectively. Then, with this information, we propose an algorithm, named Determining image Base by Matching Function Addresses (DBMFA), to determine the image base. The experimental results indicate that the proposed method can successfully determine the image base of firmware which uses LDR instruction to load function address.

The seafood and aquaculture industry in Indonesia is much less vertically coordinated. However, there are trends towards coordination in fishery value chains through processing and distribution to retail and food service customers. This study aims to examine the governance of the smoked fish value chains in the North Coast of Central Java. The study used the survey data of 52 actors along the smoked fish value chains in the North Coast of Central Java, including fisherman in Demak and Rembang regencies, various types of middleman, processor, and retailers in Semarang. The data was analyzed using value chain mapping and governance analyses. The results showed that the actors involved in the smoked fish value chains consist of fishermen, wholesalers, collectors, processors, retailers, food stalls, and restaurants. Each actor has different activities in their role to add value to differentiate smoked fish products. The results also showed that the types of value chain governance of smoke fish in the North Coast of Central Java leads to relational governance with the complex and interdependent transactions. Keywords: aquaculture, coordination, fisherman, fishery products, relational

Background: Since its introduction in 1996, the Vibrant Soundbridge (VSB) has been upgraded with several improved generations of processors. As all systems are compatible, implanted patients can benefit from new technologies by upgrading to the newest processor type available. Objectives: The aim of this study was to compare the performance of the new (current) SAMBA processor with the previous Amadé processor. Methods: Twenty subjects monaurally implanted with a VSB and the Amadé processor tested the new SAMBA processor for a trial period of 4 weeks. We measured air conduction and bone conduction thresholds, unaided thresholds, and aided free field thresholds with both devices. Speech performance in quiet using the Freiburg monosyllabic test at 65 dB SPL (S₀) was compared. The speech intelligibility in noise was determined using the Oldenburg sentence test measured in different listening conditions (S₀N_VSB/S₀N_contra) and microphone settings (omni/directional vs. adaptive directivity). Results: Word recognition scores in quiet with the SAMBA were still significantly lower than with the Amadé after the 4 weeks trial period but improved over the following year. Speech intelligibility with the SAMBA was significantly better than with the Amadé in omnidirectional mode and comparable with the Amadé in directional mode. Hence, the adaptive directionality provides an advantage in difficult hearing situations such as noisy environments. The subjective benefit was evaluated using the Abbreviated Profile of Hearing Aid Benefit and the Speech, Spatial and Qualities-C questionnaire. Results of the questionnaires demonstrate an overall higher level of satisfaction with the new SAMBA speech processor than with the older processor. Conclusion: The SAMBA enables similar speech perception in quiet but more flexible adaptation in acoustically challenging environments compared to the previous Amadé processor.

Supply chain management is a burning issue for modern industrial enterprises. To handle this issue, non-linear stochastic models are successfully applied to find the reasonable and efficient solutions. A need to develop a unique method to find the solutions to supply chain management tasks defined as stochastic mixed-integer non-linear programming tasks is determined by the limitations imposed by the general models. The sum of the total raw procurement costs from the Commodity Exchange over the defined planning horizon is taken to be the target function of the unique model, while the binary variables which show whether a purchasing order is included into the procurement plan are used for optimization purposes. Some parameters of model’s limitations are stochastic and consider the uncertainty factor and risks in supplying the required raw materials to the manufacturing site. Branch-and-bound and genetic algorithms are applied at some steps in the developed heuristic algorithm. The algorithm and the model are tested at a major timber processing enterprise in Primorsky Area. Four types of processors over three planning horizons were applied to compare the efficiency of the proposed algorithm with partial application of the genetic algorithm or branch-and-bound method. The findings analysis shows that, unlike the genetic algorithm, the unique one is more stable in terms of uncertainty of the input parameters in comparison with the branch-and-bound method. It provides the solutions in the models with a great number of variables. The algorithm is shown to be universal enough for its further modification in solving more complicated problems of the same class, containing a significantly larger number of probabilistic parameters that describe other uncertainties in the supply of raw materials. Further research is seen to include the development of the proposed algorithm to increase the rate of convergence for its better efficiency.

The theory of optimal test-control block designs provides guidance on treatments allocation in experimental units. However, it is theoretically difficult to find them; therefore, the availability of an efficient and user-friendly algorithm for finding the optimal designs is essential for both researchers and practitioners. This paper describes an algorithm for constructing efficient test-control incomplete block designs with correlated observations. In order to evaluate the algorithm, we compare our results with the optimal designs presented in some published papers. An advantage of our algorithm is its independency to the size of blocks and the structure of correlation. Also, it takes to run between 30 s and 10 min depending on the type of CPU processor and the design.

Investigations of High Throughput Computing for Event Selection Process of MuCh@CBM

Heterogeneous computing leverages more than one kind of processors to boost the performance of user-space applications with the heterogeneous programming languages, e.g., OpenCL. While some works have been done to accelerate the computations required by Linux kernel software, they are either application-specific solutions or tightly coupled with the certain computing platforms and are not able to support the general-purpose in-kernel accelerations using different types of processors. In this article, the general-purpose software framework called Kernel acceleration with OpenCL (KOCL), is proposed to tackle the problem. KOCL exposes a set of the high-level programming interfaces for the Linux kernel module developers to offload compute-intensive tasks on different hardware accelerators without managing and coordinating the platform-specific computing and memory resources. The simplified programming efforts are achieved by the developed platform management and memory models, which provide a systematic means of managing the heterogeneous hardware resources. In addition, the one- and zero-copy data-buffering schemes are offered by KOCL, so that the offloaded tasks deliver high performance on the platforms with different memory architectures. We have developed the prototype system to accelerate the Network-Attached Storage server applications. Significant performance improvements are achieved with the three different types of accelerators, i.e., the multicore processor, the integrated GPU, and the discrete GPU, respectively. We believe that KOCL is useful for the design of embedded appliances to evaluate the performance of design alternatives.

The Weighted Product method requires a normalization process because this method assumes the results of evaluating each attribute. The results of these multiplications have not been meaningful if they have not been compared (divided) with standard values. The weight for the benefit attribute functions as a positive power in the multiplication process, while the weight of the cost functions as a negative rank. The Weighted Product method uses multiplication as a linking attribute rating, where the rating of each attribute must be raised first with the corresponding weight. Weighting Product Weighted method is calculated based on the level of importance. This system requires input weight values based on prospective buyers' needs in the form of prices, RAM capacity, processor type, Harddisk capacity, and VGA (Video Graphics Array). The results of this study provide laptop recommendations according to specification requirements for prospective buyers with 100% calculation accuracy based on manual calculations and calculations on laptop selection decision support systems.

The reversible logic gate is a great choice for designing various types of optical processors due to so many advantageous aspects of it; such as low power consumption and the ability of data recovery. At first, the optical circuit of Fredkin gate, a universal reversible logic gate, is designed theoretically using a semiconductor optical amplifier (SOA)-based polarization switch, and the performance of the circuit is studied using simulated results. The frequency-encoded binary data are used to execute the operations. Subsequently, we propose the techniques of developing NOT, AND, OR, EX-OR, EX-NOR gates, and full adder circuit using reversible Fredkin gates. Finally, we develop an optical arithmetic logic unit using the proper combination of reversible Fredkin gates. The theory of nonlinear polarization rotation of the probe beam in the presence of the pump beam in SOA is adopted here. The simulated input–output spectra of the optical circuits enhance the admissibility of the proposed concept.

Special issue on applications for the heterogeneous computing era 2017

This paper introduces a new approach to building distributed-memory graph analytics systems that exploits heterogeneity in processor types (CPU and GPU), partitioning policies, and programming models. The key to this approach is Gluon, a communication-optimizing substrate. Programmers write applications in a shared-memory programming system of their choice and interface these applications with Gluon using a lightweight API. Gluon enables these programs to run on heterogeneous clusters and optimizes communication in a novel way by exploiting structural and temporal invariants of graph partitioning policies. To demonstrate Gluon’s ability to support different programming models, we interfaced Gluon with the Galois and Ligra shared-memory graph analytics systems to produce distributed-memory versions of these systems named D-Galois and D-Ligra, respectively. To demonstrate Gluon’s ability to support heterogeneous processors, we interfaced Gluon with IrGL, a state-of-the-art single-GPU system for graph analytics, to produce D-IrGL, the first multi-GPU distributed-memory graph analytics system. Our experiments were done on CPU clusters with up to 256 hosts and roughly 70,000 threads and on multi-GPU clusters with up to 64 GPUs. The communication optimizations in Gluon improve end-to-end application execution time by ∼2.6× on the average. D-Galois and D-IrGL scale well and are faster than Gemini, the state-of-the-art distributed CPU graph analytics system, by factors of ∼3.9× and ∼4.9×, respectively, on the average.

We consider the problem of assigning software processes (or tasks) to hardware processors in distributed robotics environments. We introduce the notion of a task variant, which supports the adaptation of software to specific hardware configurations. Task variants facilitate the trade-off of functional quality versus the requisite capacity and type of target execution processors. We formalise the problem of assigning task variants to processors as a mathematical model that incorporates typical constraints found in robotics applications; the model is a constrained form of a multi-objective, multi-dimensional, multiple-choice knapsack problem. We propose and evaluate three different solution methods to the problem: constraint programming, a constructive greedy heuristic and a local search metaheuristic. Furthermore, we demonstrate the use of task variants in a real instance of a distributed interactive multi-agent navigation system, showing that our best solution method (constraint programming) improves the system’s quality of service, as compared to the local search metaheuristic, the greedy heuristic and a randomised solution, by an average of 16, 31 and 56% respectively.

Automatic Software-Based Self Test Generation for Embedded Processors

New programming models have been developed to embrace contemporary heterogeneous machines, each of which may contain several types of processors, e.g., CPUs, GPUs, FPGAs and ASICs. Unlike the conventional ones, which use separate programming schemes for different processors of the machine, e.g., OpenMP for the CPU and CUDA for the GPU, the new ones tend to offer a unified programming model to abstract details of heterogeneous computing engines. One such programming model is Halide that is designed for high performance image processing. Halide programmers are allowed to map data and computation to either the CPUs or GPUs through high-level C++ functions, which are converted to various code targets, including x86, ARM, CUDA, and OpenCL, by the Halide compiler. Nevertheless, it becomes complex when the programmers attempt to write a Halide program for cooperative computation on both the CPU and GPU. In this work, we propose the synergistic computing framework that extends Halide to improve program execution performance. Several key issues are tackled, including data coherence, workload partitioning, job dispatching and communication/synchronization, so that the Halide programmers are allowed to take advantage of the heterogeneous computing engines with the two developed C++ classes, one is for static workload partitioning/dispatching and the other is the dynamic counterpart. Furthermore, optimizations are developed to improve performance by generating adequate the CPU code, and eliminating extra memory copies. We characterize and discuss the performance of two image processing programs and our framework on the heterogeneous platforms, i.e., Android Nexus 7 smartphone and x86-based computers. Our results show that significant performance gain can be achieved while the CPU and GPU execute a program synergistically with the proposed framework.

Many emerging applications such as the Internet of Things, wearables, implantables, and sensor networks are constrained by power and energy. These applications rely on ultra-low-power processors that have rapidly become the most abundant type of processor manufactured today. In the ultra-low-power embedded systems used by these applications, peak power and energy requirements are the primary factors that determine critical system characteristics, such as size, weight, cost, and lifetime. While the power and energy requirements of these systems tend to be application specific, conventional techniques for rating peak power and energy cannot accurately bound the power and energy requirements of an application running on a processor, leading to overprovisioning that increases system size and weight. In this article, we present an automated technique that performs hardware–software coanalysis of the application and ultra-low-power processor in an embedded system to determine application-specific peak power and energy requirements. Our technique provides more accurate, tighter bounds than conventional techniques for determining peak power and energy requirements. Also, unlike conventional approaches, our technique reports guaranteed bounds on peak power and energy independent of an application’s input set. Tighter bounds on peak power and energy can be exploited to reduce system size, weight, and cost.

Many emerging applications such as IoT, wearables, implantables, and sensor networks are power- and energy-constrained. These applications rely on ultra-low-power processors that have rapidly become the most abundant type of processor manufactured today. In the ultra-low-power embedded systems used by these applications, peak power and energy requirements are the primary factors that determine critical system characteristics, such as size, weight, cost, and lifetime. While the power and energy requirements of these systems tend to be application-specific, conventional techniques for rating peak power and energy cannot accurately bound the power and energy requirements of an application running on a processor, leading to over-provisioning that increases system size and weight. In this paper, we present an automated technique that performs hardware-software co-analysis of the application and ultra-low-power processor in an embedded system to determine application-specific peak power and energy requirements. Our technique provides more accurate, tighter bounds than conventional techniques for determining peak power and energy requirements, reporting 15% lower peak power and 17% lower peak energy, on average, than a conventional approach based on profiling and guardbanding. Compared to an aggressive stressmark-based approach, our technique reports power and energy bounds that are 26% and 26% lower, respectively, on average. Also, unlike conventional approaches, our technique reports guaranteed bounds on peak power and energy independent of an application's input set. Tighter bounds on peak power and energy can be exploited to reduce system size, weight, and cost.

This paper presents an algorithm for finding carriers of frequency-modulated (FM) and amplitude-modulated (AM) electromagnetic (EM) emanations from computer systems. Computer systems create EM emanations across the RF spectrum making it difficult, error-prone, and time consuming to find the relatively few emanations that expose sensitive information. One of the most common and simplest mechanisms for information leakage occurs when an amplitude or a frequency of an existing strong signal (e.g., a processor or memory clock) is amplitude or frequency modulated by a system activity. If the system activity can be linked to sensitive information, this results in information leakage. We present an algorithm for automatically finding these AM and FM signals, demonstrate the algorithm's performance on several different types of processors and systems (desktop, laptop, and smartphone), and compare the results to an exhaustive manual search. We also verify that all signals identified by the algorithm can be traced to plausible unintentional modulation mechanisms to illustrate that these signals can potentially cause information leakage. This algorithm can be an important tool for system designers to quickly identify circuits that are leaking sensitive information.