Advanced Semiconductor Engineering (Taiwan)

This study investigates the non-uniformity (NU%) of copper deposition in a three-dimensional panel electroplating cell using COMSOL Multiphysics® 6.1 (COMSOL Inc., Burlington, MA, USA). To ensure the accuracy of the simulated current efficiency, the modeling was initially conducted on the electrodeposition of nanoscale metal wires (Nanowires, NWs) using the Finite Element Method (FEM) in COMSOL. After verifying that the simulation accurately reflected the current efficiency at the nanoscale, the model was scaled up to simulate full-sized panel-level electroplating. Various simulation conditions were explored, including two dimensional and three dimensional, electrode kinetics equations, electrolyte compositions, and current densities. The effects of these parameters on current efficiency and deposition uniformity were analyzed to develop a highly accurate COMSOL model. In terms of electrode kinetics, the study compares the advantages and limitations of secondary current distribution and tertiary current distribution models found in the previous literature, and evaluates their simulation results. Furthermore, to reflect the experimental condition where a pre-deposited copper seed layer was applied to reduce internal cathode resistance, the electrode shell physics module in COMSOL was implemented to simulate the potential distribution across the cathode surface. The results confirm that the numerical model using the tertiary current distribution provides more accurate predictions compared to the conventional secondary current distribution approach.

In this work, we demonstrate a 3D-SiP Power IC packaging approach that achieves a 20 % reduction in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$x-y$</tex> footprint while maintaining electrical performance. The vertical stacking of components allows for greater power density and compact system integration, making it suitable for nextgeneration power modules. Electrical measurements confirm no degradation in efficiency, indicating that the miniaturization does not compromise functional performance. However, thermal challenges emerge due to increased power density and limited heat dissipation paths. To address this, comprehensive thermal simulations were conducted to analyze heat accumulation and identify critical hot spots. Optimized thermal management solutions were implemented, including enhanced heat spreading layers and improved thermal vias. These improvements reduced the junction-to-board thermal resistance (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{\Psi}_{\text {JB) }}$</tex>) from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$31.62^{\circ} \mathrm{C} / \mathrm{W}$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$23.35^{\circ} \mathrm{C} / \mathrm{W}$</tex>, effectively mitigating thermal impact and ensuring reliable operation. The proposed solution highlights the trade-offs and benefits of vertical integration in power ICs and provides a guideline for future compact power system designs.

Abstract Traditional failure analysis (FA) methods face growing challenges due to the increasing miniaturization and complexity of modern semiconductor devices. In particular, the detection of cracks in the extreme low K layers of flip-chips, utilized in advanced packaging architectures at the back end of line (BEOL), is challenging. To improve detectability of these defects, we propose an AI-based image enhancement workflow, specifically tailored to improve scanning acoustic microscopy (SAM) images. By applying a Deep CNN with Skip Connections and Network in Network (DCSCN) model to lowresolution C-scan SAM images, we are able to improve perceptual quality of images. The approach boosts resolution dependent analysis like AI-based object detection and classification as well as decreases significantly SAM scanning time. Our work demonstrates that AI-based image enhancement can significantly improve FA workflows, offering a robust and efficient solution for modern semiconductor analysis.

In this study, the three shapes of dielectric resonator antennas (DRAs) with and without a uniplanar compact electromagnetic bandgap (UC-EBG) structure were designed and investigated for 20~40 GHz millimeter-wave ranges. The trapezoidal and pyramidal (prism) DRAs were proposed to compared with a rectangular DRA. Their impedance bandwidth from -10 dB of scattering parameter S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</inf> and gain are calculated and compared. A unit cell of the UC-EBG structure is designed to obtain its frequency bandgap to coincide with the resonant frequency of DRA. It was found that in the simulated frequency range, the pyramidal shape exhibited a wider bandwidth than the trapezoidal configuration but narrower than the rectangular DRA. It is observed that the integration of UC-EBG significantly broadens the impedance bandwidth and improves the front-to-back ratio. However, a slight reduction in peak gain and radiation efficiency is also noted, which can be attributed to the redistribution of electromagnetic energy within the structure. Comparative results indicated that the UC-EBG is effective in enhancing bandwidth and radiation characteristics, but a trade-off exists between bandwidth enhancement and gain performance.

To address thermo-mechanical challenges in power module substrates, this study investigates three Insulated Metal Substrate (IMS) designs with varied copper layer thicknesses. Finite element analysis (FEA) was employed to predict thermal resistance and mechanical warpage, followed by experimental validation through warpage measurements and dielectric insulation tests. The objective is to identify an optimal IMS configuration that balances thermal performance with mechanical reliability, thereby providing a robust substrate solution for next-generation power electronics.

Abstract A more systematic, multiscale characterization of the mechanical properties of lignocellulosic materials, such as wood and bamboo, is needed so that manufacturers can better tailor their properties for specific end-uses. Nanoindentation was used to assess the mesoscale elastic modulus ( E S N I ${E}_{S}^{NI}$ ) and Meyer’s hardness ( H ) of secondary cell wall layers (SCWL) in Moso bamboo, and S 2 SCWL and compound corner middle lamella (CCML) in loblolly pine. The anisotropic SCWL was tested in both longitudinal and transverse directions. The effects of moisture content (MC) were studied by testing specimens conditioned between 1 % and 92 % relative humidity (RH). Both pine and bamboo SCWL exhibited many of the same features in their MC- and orientation-dependent E S N I ${E}_{S}^{NI}$ and H results, which suggested that the features were general characteristics of SCWL from different plants. A new transition in plasticity was observed around 2–4 % MC in which the SCWL transverse H had a sudden 20 % decrease. For comparison to literature plasticity S 2 SCWL uniaxial compression flow stress ( σ ) measurements made using micropillar compression testing, a H -derived uniaxial compression flow stress ( σ H ) was calculated using established methods. The σ H compared well to the literature σ , which supported that both H and σ can be used to similarly study plastic deformation mechanisms.

This <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Perspective</i> builds upon insights from the National Institute of Standards and Technology (NIST)-organized workshop, “Materials and Metrology Needs for Advanced Semiconductor Packaging Strategies,” held at the 35th annual Electronics Packaging Symposium in Binghamton, NY, on September 5, 2024. It outlines critical challenges and opportunities related to polymer-based “soft” materials in advanced semiconductor packaging, with emphasis on polymer science, measurement science (metrology), and the strategic development of Research-Grade Test Materials (RGTMs). These efforts, led by the NIST CHIPS team, aim to advance the fundamental understanding of structure–property–processing relationships, promote standardized guidelines and innovative methods for material characterization, and accelerate the development, qualification, and adoption of next-generation packaging materials. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Perspective</i> also distills key insights from the panel discussion with industry experts, emphasizing the need for close collaboration among materials scientists, process engineers, and metrology experts to enable a holistic strategy, further highlighting the importance of cross-sector partnerships among industry, academia, and government to address pressing challenges in packaging materials and processes.