Beijing Microelectronics Technology Institute

Purpose This study aims to accurately predict and suppress the multipactor effect which is critical for aerospace microwave switches. Design/methodology/approach This paper presents a methodology for designing L-band aerospace high-power microwave switch using combination of simulation and experimentation to improve the power threshold. First, the secondary electron yields of different metal material coatings and Alodine treatment are measured experimentally for subsequent simulations. Second, the L-band aerospace high-power microwave switch is modeled and simulated. And the effects of surface coating design and gap design on the multipactor power threshold of high-power microwave switch are discussed. Finally, the experimental system is used to measure and confirm the influence of coating and gap on the multipactor power threshold. Findings The influence of coating and gap design on multipactor threshold of microwave switch is demonstrated by simulation and experiment. The conclusions show that the surface coating and gap design have large effect on the microwave switch multipactor thresholds, and the good agreement is confirmed using numerical simulations and experimental results. Originality/value The power threshold of L-band aerospace microwave switch designed in this paper is improved from 200 W @ 1 GHZ to 1000 W @ 1 GHZ.

To meet the energy-saving requirements of user equipment (UE) operating in Radio Resource Control idle/inactive states (RRC_IDLE/RRC_INACTIVE) in the 3rd-Generation Partnership Project (3GPP) 5G-Advanced (5G-A) networks, the New Radio (NR) downlink paging procedure relies on periodic monitoring and frequent synchronization signal block (SSB) measurements, which wastes energy when no paging arrivals occur. Meanwhile, heterogeneous Quality of Service (QoS) constraints make it difficult for fixed-parameter Idle Discontinuous Reception and Paging Early Indication mechanisms (IDRX/PEI) to balance energy, delay, and reliability. This paper develops a UAV-assisted 5G-A paging control framework that maps services into multiple QoS classes and models QoS violation risk and system energy consumption under unified accounting, including UE monitoring/reception energy and unmanned aerial vehicle (UAV) forwarding energy. We then propose a QoS-aware risk-driven paging strategy: an offline Long Short-Term Memory (LSTM) predictor is trained to estimate the time-to-next-arrival (TTNA) of paging events and produce a bounded urgency/risk signal to initialize class-dependent thresholds, while online triggering and QoS-feedback-based threshold adaptation regulate the empirical violation rate toward target constraints under varying loads, enabling a controllable energy–delay trade-off. A simulation-based evaluation is conducted to compare the proposed method with representative baselines (Enhanced Paging Monitoring (EPM), Split Paging Occasion (SPOP), and Predicted Paging Early Indication (PPEI)) and to examine the impact of SSB overhead and UAV relaying on the energy–delay–reliability trade-offs.

A novel Lateral Strained Superjunction (LSSJ) with low specific on-resistance (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub>) is proposed and simulated in this letter. The partially relaxed Silicon-Germanium (Si<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub>Ge<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub>) layer, as the P-type pillars of LSSJ, induces biaxial tensile stress in the N-type Silicon (Si) pillars to enhance electron mobility. The Si<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub>Ge<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> pillars across the drift region mitigates the lateral stress relaxation, enabling the high-voltage application of LSSJ. The charge compensation layer eliminates the substrate assisted depletion effect and modulates the surface electric field so as to improve the breakdown voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BV</i>). A balanced superjunction structure with P-type Si<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub>Ge<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> pillar and N-type Si pillar is achieved. The simulation results show that, for the lateral diffused metal-oxide-semiconductor (LDMOS) with a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BV</i> above 400V, LSSJ exhibits a 20% reduction in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> and a slight 2% degradation in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BV</i> compared to the SJ with a buried step doping (BSD) layer, thus resulting in a 18% improvement in figure-of-merit (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FOM</i>). The LSSJ realizes a superior performance and is suitable for the LDMOS with a SJ drift region, especially for the next-generation narrow-pitch SJ, which faces the degradation in carrier mobility.

We present a stable embedded discontinuous Galerkin (EDG) method for scalable electrothermal simulation of 3D semiconductor devices. The framework extends the robust hybridized discontinuous Galerkin method developed for purely electric paradigm to resolve fully coupled electrothermal drift-diffusion equations, addressing a critical gap in existing harmonic-averaging formulations that lack non-isothermal current modeling. It is believed that for the first time, we derive a consistent discretization of thermally coupled current terms within the EDG scheme, ensuring stability under strong convection and Joule heating. A parallel solver is further developed and implemented via the JAUMIN framework using domain decomposition, enabling extreme-scale 3D simulations of semiconductor devices. The validations on p-n junctions, NLDMOSFET and multi-finger FinFET demonstrate superior Newton convergence and comparable accuracy in comparison with that of commercial software COMSOL. It can achieve 79.2% strong scaling efficiency (20×cores) and 59.0% weak scaling efficiency (8× problem size) in the 8-Finger FinFET electrothermal simulations.

Abstract 2D materials provide a versatile platform for developing memristor‐based in‐memory computing systems, with potential to address some limitations of conventional von Neumann architectures. However, meeting the stringent requirements for precision, stability, and energy efficiency in neural network hardware remains a challenge due to the intrinsic properties of many 2D materials. In this work, a controllable ultraviolet ozone (UVO) treatment is introduced to engineer the properties of 2D indium selenide (InSe) by introducing a tailored combination of defects, amorphous regions, and oxidized phases. This modification improves the structural stability and vertical conductivity of InSe, and promotes ion migration, enabling a transition from non‐switching to stable nonvolatile resistive switching (RS) behavior. The resulting memristors exhibit uniform RS characteristics, with low variability in switching voltage (5.8%) and a tunable on/off ratio ranging from 10 2 to 10 5 . In addition, the devices demonstrate sub‐20 ns switching speeds and can emulate artificial neural networks (ANNs) with recognition accuracy comparable to software‐based implementations. Hardware‐based convolutional image processing with improved power efficiency is further demonstrated, underscoring the potential of UVO‐InSe memristors for energy‐efficient neuromorphic computing applications.