Centro Universitário da FEI

This work presents a comparative statistical investigation into the enhanced ionizing radiation hardness between the Octagonal (OnM) and Conventional (CnM) MOSFETs under X-ray environment. The primary objective is to quantify the robustness of OnM across varying Total Ionizing Dose (TID) levels and biasing conditions. A comprehensive statistical framework was applied, integrating Z-score normalization, K-means clustering, Cramer’s V, and association analysis to evaluate device variability. Experimental results demonstrate that OnM devices exhibit significantly superior electrical consistency, evidenced by a markedly lower coefficient of variation (C.V.) for the on-state drain current (0.1020 vs. 0.5689) and higher cluster cohesion compared to CnM counterparts. Furthermore, a Bootstrap validation confirmed the high stability of OnM clusters (Jaccard coefficient minimum value of 81.2%), reinforcing their deterministic behavior. These findings statistically validate the OnM intrinsic resilience, supporting its suitability for reliable operation in mission-critical space, nuclear, and medical applications.

<div class="section abstract"> <div class="htmlview paragraph">The growth of the electric vehicle market has driven the advancement of technologies related to energy storage and lithium-ion cells, which stand out for their fast charge and discharge capabilities, high energy density, and long service life. This paper proposes a thermal control strategy for lithium-ion battery packs using the Active Disturbance Rejection Control (ADRC) method. The model is developed in Simcenter Amesim software, using cylindrical 21700 cells in a pack equipped with a water-cooling system, and was adapted for export in FMU format and integrated into MATLAB/Simulink, where the control algorithms were designed and simulated. From step input tests, a first-order transfer function was identified with a fitting of 97.67%, supporting the adoption of a first-order ADRC. The tests involved scenarios with changes in temperature reference and current disturbances typical of vehicle operation. Results indicate that ADRC performs satisfactorily in temperature tracking, even under actuator saturation, and particularly excels in disturbance rejection, outperforming the proportional-integral-derivative (PID) controller in speed and precision. Furthermore, ADRC proved robust to system degradation—an essential feature in the thermal management of batteries subject to aging. The proposed approach shows promise for real-world applications, offering thermal stability and extended system lifespan. For future work, experimental validation through Hardware-in-the-Loop (HiL) is suggested.</div> </div>

<div class="section abstract"><div class="htmlview paragraph">This study presents the results of applying a Lean Six Sigma-based analytical approach to optimize the manufacturing of automotive coatings, specifically in a PU primer filling process. Through production flow mapping and the Define, Measure, Analyze, Improve, and Control (DMAIC) methodology, unplanned stoppages in the filling line were significantly reduced, addressing critical inefficiencies in automotive coating production. The research was driven by the need to enhance manufacturing productivity and ensure process reliability in the production of coatings used in the automotive sector. To achieve this, Quality Management tools, such as Pareto Analysis and the Cause-and-Effect Diagram, along with Lean Manufacturing techniques, including Kaizen Blitz, were applied. These methods facilitated the identification and mitigation of key causes of unplanned downtime, improving process efficiency and reliability. The results demonstrated a significant reduction in downtime, enhanced operational efficiency, and an increase in Overall Equipment Effectiveness (OEE). Furthermore, the implementation of Reliability-Centered Maintenance (RCM) practices contributed to process stability and improved failure prediction, ensuring higher consistency in automotive coating production. This study highlights that integrating lean methodologies with data-driven analysis is a highly effective strategy for improving manufacturing performance in the automotive industry, reducing operational costs, and strengthening supply chain resilience for automotive coating manufacturers.</div></div>

This study presents a data-driven approach for smart tire management through the application of unsupervised machine learning techniques. Using a real-world dataset comprised with synchronized records collected at 1 Hz from a sensor-equipped fleet vehicle, the research investigates how the use of clustering algorithms – K-Means and BIRCH with Agglomerative Clustering – can be employed to identify distinct operational stages in the usage cycle of tires. A comprehensive descriptive analysis was first conducted to understand the behavior and correlations among pressure, temperature, and speed data. The clustering analysis, applied both globally and by individual tire positions, revealed that the optimal number of clusters can vary depending on the tire’s location. The findings highlight the importance of position-aware tire analytics and support the development of intelligent tire management systems capable of optimizing performance, enhancing safety, and extending tire lifespan.

ABSTRACT The growing demand for sustainable solutions has intensified interest in approaches that enable the transition from linear to circular economic models. In this context, this study proposes the development of a conceptual framework that integrates blockchain technology to support the implementation of circular practices. The circular economy aims to reduce waste and maximize the retention of resource value throughout its life cycle. However, its operationalization faces challenges such as a lack of traceability, limited trust among supply chain actors, and insufficient transparency in shared information. Blockchain technology, which enables secure, decentralized, and immutable recording and sharing of data, is a promising alternative to overcome these barriers. Through a systematic literature review, the objective is to propose a conceptual framework that explains how blockchain functionalities can support the execution of circular practices across different stages of the supply chain. The framework is grounded in three theoretical lenses: The Diffusion of Innovation Theory, Institutional Theory, and Transaction Cost and Network Effect Theory. It is structured around three main constructs: blockchain (with key functionalities such as traceability, smart contracts, and tokenization), circular economy practices (based on the hierarchy of the 10rs), and a circular supply chain (focusing on integration, reverse logistics, and sustainability certification). The methodology involved a systematic literature review following PRISMA guidelines, resulting in the analysis of 67 peer‐reviewed articles. The findings provide theoretical and practical insights into how blockchain can enable traceability, transparency, automation, and cost reduction in circular supply chains, thereby accelerating the adoption of sustainable and efficient business models.

In this work, the performance of a Common Source Current Mirror based on Junctionless Nanowire Transistors was analyzed at different temperatures. In that approach, the configurations were biased at the same conduction level, presenting a current transfer ratio and output conductance that do not vary significantly with temperature. This low variance with temperature seems to be a consequence of the phonon and neutral impurity scattering mechanisms neutralizing each other, resulting in a low electron field mobility that is almost constant for all temperatures.

The advance of technology demands an extreme miniaturization of electronic devices, reaching prohibitive levels from the point of view of the short channel effects (SCEs) as well as manufacturers' limitations. One important cumbersome task in ultimate devices consists of the formation of the source and drain regions that demand the variation of doping types and concentrations in several orders of magnitude in very short dimensions. Some techniques are proposed to overcome these unwanted effects, such as the introduction of multi-gate structures as well as the use of SOI technology that isolates the active silicon layer from the substrate. Even though, in ultimate technological nodes this is still a major issue.Aiming to minimize these unwanted effects, Junctionless Nanowire Transistors (JNTs) were proposed. They consist of a high-doped nanowire with the same doping type in the source/channel/drain regions, commonly surrounded by an oxide/metal stack on an SOI wafer. These devices usually have multiple gates, improving their gate electrostatic control over the channel charges and improving the immunity to SCEs. As no junctions of the source and the drain to the channel are formed, this device is manufactured in a way that the difference between the channel and gate work functions makes the device fully depleted, blocking the current flow.JNTs can be fabricated with dielectric spacers, that form an extension between channel and source/drain regions. This permits the depletion region due to the gate to be extended towards the source and drain regions in the off-state and in partial depletion regime, making the effective channel length LEFF longer than the mask channel length and reducing the SCEs.The estimation of LEFF is not a simple task, and some experimental methods have been proposed in the literature to extract it. One of the methods, based on the total gate capacitance extraction, can only be applied to large devices due to the limitations of measuring the extremely low capacitances observed in short and narrow devices, while another one, based on the subthreshold slope (SS) has only been validated for low drain bias (VDS). However, studies are still needed to evaluate and improve these methods. So, the objective of this work is to study and extract the LEFF of JNTs through SS, for high VDS bias when the SCEs are present.This work considers experimental devices provided by CEA-LETI, with channel lengths of 30 and 100 nm, source and drain lengths of 15 nm, effective gate oxide thickness of 1.5 nm, buried oxide of 150 nm, width of 20 nm, height of 10 nm and doping concentrations of 5 x 1018 and 1 x 1019 cm-3 operating at 300K.To extract the SS of the devices, the drain current (ID) curves were obtained as a function of the gate voltage (VGS), as shown in Fig. 1(A) and (B) for P- and N-type MOSFETs, respectively. In the sequence, SS was extracted through the plateau obtained by the inverse of the derivative of the logarithm of ID with respect to gate voltage as presented in Fig. 2. LEFF has been extracted for experimental devices through the relationship between a long and a short device SS, as indicated in Eq. (1). This equation assumes that the minimum potential is located at the center of the channel of the device, which is valid for low drain bias. However, for high VDS bias (for 500 mV or higher) the minimum potential moves towards the source side of the transistor. So, aiming to allow its application in devices biased with high VDS, the SS needs to be divided by a factor that represents the rate of the minimum potential shift towards the source with VDS increase. In the present work, this factor was experimentally determined as 1.08.The LEFF of the devices is exhibited in Table 1, which presents the comparison between the LEFF obtained by Eq. (1) and Eq. (2), which consists of an analytical expression for the estimation of LEFF based on the physical characteristic of the devices considering different biasing conditions. However, as there could be imprecision between the target and actual characteristics of the devices, Eq. (1) was proposed to enable LEFF estimation directly from experimental measurements. The LEFF was extracted for different doping concentrations and doping types and resulted in LEFF higher than the mask channel length in all cases. The method is able to capture the dependence on doping concentration and showed adequate results when applied for VDS values, showing a maximum error of 16% with respect to the analytical model of Eq. (2). Figure 1

The evolution of the field effect transistor technology has led to the reduction of the device dimensions to a few tenths of nanometers or even smaller. As the devices' dimensions are reduced, the occurrence of short-channel effects becomes unavoidable and degrades, to some extent, the electrical characteristics of the devices even when multiple gate or nanowire technologies are applied. This effect contributes to the variability of the devices, and, as a consequence, to its reliability.In ultimate devices such as nanowire FETs, reliability is inherently important since small variations in the electrical parameters, e.g. the drain current or the threshold voltage, can significantly affect the device performance in a circuit application. Several reliability issues such as Self-Heating Effect (SHE), Negative-Bias Temperature Instabilities (NBTI), Low-Frequency Noise (LFN), Random Telegraph Noise (RTN), and Time-Dependent Dielectric Breakdown (TDDB) are geometry-dependent and become more important for short-channel devices. Most of these parameters are strongly affected by the occurrence of defects or traps in the interface between the active region and gate dielectric. Thus, the analysis of the quality of the semiconductor-dielectric interface has become increasingly important and can be performed through different techniques. Each of them demands different facilities and can deliver different information from DUTs.Low-Frequency Noise Several is one of the most complete analyses that can be performed in terms of reliability in ultimate devices, as it enables access to several parameters with respect to traps’ characteristics. By the fundamental shape of the drain current noise spectral density (SId) as a function of the frequency (f), it is possible to verify the presence of trap centers, which overwhelm the overall noise, such that SId presents a plateau followed by a 1/f2 decay with frequency increase, the so-called G-R noise, instead of the standard 1/f shape, as shown in Fig. 1 for junctionless transistors. Also, through some mathematical manipulation in the case of 1/f shape, one can extract the active trap density (Nit), its dependence on bias conditions (Fig. 2(A)), and the trap depth inside the dielectric layer (Fig. 2(B)). If structures with different geometrical characteristics, such as different dielectric thicknesses need to be compared, it is useful to calculate the Gate Noise Parameter (GNP), which enables a fair comparison between different samples. This parameter can also be used to indicate the nature of the energy distribution of traps. For samples with 1/f2 aspect, where G-R noise is dominant, the activation energy of the dominant trap center can also be extracted through the measurement of LFN as a function of the temperature by plotting the Arrhenius curve. However, the low-frequency noise characterization requires a specific setup, including an LFN analyzer, Low-Noise Amplifiers (LNAs), and, frequently, strategies to compensate for the instrumentation background noise. Besides that, there are some situations in which the determination of Nit through LFN is difficult, as in the case of NBTI occurrence, where traps are generated along time.Therefore, other techniques can be applied either to extract parameters not easily obtained through LFN or to avoid the use of a specific setup. In this case, it could also be possible to extract trap density through capacitance curves, where a C-V meter is needed, or even through current curves (ID) as a function of time (t) or gate bias (VG). The ID-t and ID-VG characteristics can be an alternative to estimate active trap density and its profile along the bandgap, for example. Through a charge-pumping-like method, a pulsed signal can be applied in the gate of a transistor. Thus, the drain current will follow the gate bias, and the rise and fall times of ID can be associated with the occupation and release of traps, allowing for an estimation of Nit. It is worth mentioning that the accuracy of this estimation is better for devices with larger total trap density (N0) as stated in Fig. 3. Finally, there are methods that permit the extraction of active trap density and its profile along bandgap directly through ID-VG curves. In long devices, the active trap density can be estimated through the behavior of subthreshold swing, which is directly correlated to Nit and, in some ultimate devices, such as junctionless nanowire transistors, the variation of the substrate bias permits extraction of Nit profile along the bandgap (Fig. 4). This is only possible because, in these devices, the surface potential is not pinned at twice the Fermi potential in the conduction regime as it occurs in inversion mode transistors. Figure 1

The optimization of passenger car efficiency is an important contribution to GHG emissions mitigation. This global warming concern is pushing technological solutions to reduce vehicle fuel consumption and consequently CO2 emissions. In this work, the impacts of engine lubricants with lower viscosity and friction modifier additive in a light-vehicle with a spark ignition engine were numerically simulated and experimentally validated. The substitution of a baseline 5W40 lubricant by a lower viscosity 5W20 proposal resulted in 2.9% lower fuel consumption in a combined cycle. This fuel consumption improvement is enhanced to 6.1% with a 0W16 lubricant with friction modifier. A 1D simulation model based on lubricant temperature and viscosity impact on engine friction was developed and presented good experimental correlation in combined cycle for 5W20, showing a 7% lower fuel consumption advantage than the experimental results. The numerical simulation advantage was 38% lower than experimental results for 0W16 that contains friction modifier, as the additive impact was not considered in this mathematical model.

We investigate the implementation of triple modular redundancy (TMR) with different number of voters in a softcore RISC-V microprocessor to mitigate radiation-induced faults in the configuration memory (CRAM) of SRAM-based FPGA. The case-study microprocessor is the Steel Core implemented in AMD Xilinx 7-Series/Zynq-7000 device, executing benchmark software on the FreeRTOS operating system. We implemented coarse-grained TMR (CGTMR) and fine-grained distributed TMR (FGDTMR) using an automated redundancy and voter insertion tool. TMR is used in combination with memory scrubber featured by the FPGA hardware, which uses error correction codes (ECC) to revert radiation-induced faults in CRAM. Fault injection in CRAM emulating radiation-induced faults is used to evaluate the benefits of both TMR and ECC. Under fault injection, combining the fault masking capability of TMR with the self-healing by ECC, improved mean time between failures (MTBF) up to 5×. ECC alone did not improve significantly the fault tolerance. Without ECC, FGDTMR improves MTBF in 2×, but at a higher cost in circuit area and resources usage. When combined with ECC, the CGTMR provides fault tolerance comparable to FGDTMR but with 30% less resources usage.