- Conference Article
- 10.1109/csitss67709.2025.11295802
Design and Timing Analysis of LFSR with Variable Order of Interleaving Sequence
- Nov 20, 2025
- B P Swathi + 4 more +4
In cryptography and communication system applications, Linear Feedback Shift Registers (LFSRs) are commonly used for pseudorandom number generation due to their simplicity and capability of generating long periodic sequences. But the linear characteristics of basic LFSRs weaken their resistance to cryptanalytic attacks. This work presents a new interleaved LFSR system design that promotes randomness and security through output combination from various LFSRs, each governed by distinct primitive polynomials of equal degree, using a dynamic interleaving process. Control-based sequence determines interleaving order, substituting the fixed cyclic approach with a programmable strategy. Register Transfer Level (RTL) implementation is designed using Verilog and verified for correctness through Cadence tools, supplemented with static timing analysis conducted on the synthesized gate-level netlist. The results confirm functional correctness and demonstrate that the design meets setup and hold timing constraints, with a setup slack of 4.758 ns and a hold slack of 0.164 ns, thereby validating the effectiveness and reliability of the proposed interleaved LFSR approach.
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