Institute of Microelectronics

As technology nodes in integrated circuit manufacturing continue to shrink, the impact of wafer and reticle stage vibrations on lithographic imaging quality has become increasingly pronounced. Focusing on extreme ultraviolet lithography for contact hole patterns, this work systematically investigates the influence of stage vibrations on imaging performance with a rigorous lithographic imaging model and numerical simulations. Dynamic stage vibrations are incorporated into a conventional static imaging model to establish a more realistic dynamic imaging framework, and optical proximity correction (OPC) is used to emulate advanced-node process characteristics across different patterns. Results indicate that, as the target feature size decreases, the sensitivity of imaging to vibration increases significantly, and larger vibration amplitudes lead to a clearly nonlinear degradation of imaging quality. A comparative analysis of imaging performance and vibration robustness for different critical dimensions shows that bright-field masks exhibit slightly inferior vibration tolerance, whereas dark-field masks provide superior robustness for dense patterns. Building on these findings, an OPC optimization strategy incorporating moving standard deviation is proposed, offering a feasible approach to mitigating the adverse effects of stage vibrations on lithographic imaging.

In this letter, we present an epi-Si channel ferroelectric vertical gate-all-around (FEVGAA) FET featuring a gate and channel interlayer (G.IL/C.IL) co-design to achieve a wide memory window (MW) and robust reliability. The performance enhancement stems from two synergistic mechanisms: (1) gate-injected charges (Q<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tG</sub>) induced by the G.IL, and (2) C.IL nitridation, which raises trap formation energy while introducing positive fixed charges to improve endurance, retention, and read-disturb immunity. Enabled by this strategy, a record MW of 3.5 V is realized, representing a 7.7X expansion compared to the reference FE-only device. The maximum ISPE slope also improves 8.8X. Notably, the device endures 5×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> cycles with negligible I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> degradation at the large MW state. Endurance is further extended to 5×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> cycles with a nanosecond-level high operating speed. Moreover, the retention loss after 10 years is only 2.8%. In addition, the device exhibits strong immunity to read disturb for 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cycles. This gate stack design expands the application of FEVGAA devices in high-density non-volatile memory.

Transformer models excel at natural language processing tasks but are challenging to deploy on edge devices due to high memory and computation demands. To address this, we proposed an energy- and area-efficient transformer accelerator. We identify ‘0’ bits in positive and ‘1’ bits in negative 2’s complement activation values as bipolar sparsity. This form of sparsity shares a larger proportion than the traditional bit-level sparsity in transformer models. We propose a bipolar sparsity compressor (BSC) together with a bipolar processing element (BPE) to detect and skip the bipolar sparsity in a bit-group (BG) level during the inference. It reduces a large proportion of ineffective computations and improves throughput. The significant sparsity scheduling (SSS) dynamically adjusts broadcast settings based on BG-level sparsity ratios, balancing the sparsity skipping and memory access. Furthermore, an importance approximate gating (IAG) filters out unimportant tokens/heads during the attention computation by reusing sparsity information from the BSC, further reducing processing latency and energy consumption. Implemented in a 28nm process, the proposed accelerator achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.62\times $</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$12.43\times $</tex-math> </inline-formula> throughput improvements on RoBERTa-B and GPT2-xl, respectively. The area efficiency reaches up to 3.51 TOPS/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> due to skipping a large proportion of bipolar sparsity, reaching <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.83\times$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.85\times $</tex-math> </inline-formula> higher compared with the state-of-the-art approximate computing accelerator and the computing in memory accelerator on the benchmark model.