MediaTek (Taiwan)

This work presents MADiC, a 3nm 0.338mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> diffusion accelerator for generative image editing on edge devices. MADiC features design-time L1/L2 memory optimization, cross-loop feature map allocation with write-over-read relaxation, and activation-aware input preloading with concurrent resizing. Operating at 0.575V and 546MHz, it delivers 7.4TOPS/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 17.4TOPS/W when running the Diffusion ConvNet model.

Affine frequency division multiplexing (AFDM) has emerged as a promising Doppler-resilient waveform for high-mobility communications. To leverage its full diversity, we develop a real-valued expectation propagation (rEP) detector. However, its complexity is prohibitive, particularly in fractional Doppler scenarios with power leakages. Hence, we propose a Preconditioned Conjugate Gradient-based Message Passing-Initialized Approximated-Variance rEP (PCG-MPI-AVrEP), which employs diagonal reciprocity and single-pass MP for variance approximation. Based on channel structures, an incomplete LDL preconditioner is designed to accelerate convergence during PCG-based exact mean updates, reducing iterations by at least 86% compared to CG. Simulation results demonstrate that PCG-MPI-AVrEP significantly outperforms prior detectors while maintaining quadratic complexity with respect to subcarriers.

Neural networks have demonstrated superior performance over rule-based and model-based approaches in processing noisy sensing data. However, their substantial computational and energy demands hinder deployment in battery-powered embedded systems. Computing-in-Memory (CIM) devices offer a promising alternative by significantly reducing energy consumption. Prior work [2] achieves this by leveraging a non-von Neumann architecture, which minimizes data movement between memory and compute units, thereby mitigating the memory wall bottleneck. Despite these advantages, analog CIM (ACIM) systems face several key challenges, including analog noise, limited numerical precision, and increased hardware complexity. While cloud-based neural networks are still dominant, emerging applications increasingly demand real-time, privacy-preserving inference on-device. For instance, facial authentication requires local execution on edge devices to ensure low-latency responsiveness and to protect user privacy. CIM architectures are particularly well-suited to these scenarios due to their tightly integrated memory-compute structure, offering low-latency and energy-efficient inference capabilities.

This work presents a Transformer accelerator with a large-language-model-friendly (LLM-friendly) architecture, supporting a multi-head adaptable computation scheme. The accelerator features (1) the first token-lengthindependently fully-pipelined computing-in-memory (CIM) network with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$27.1-42.3 \%$</tex> energy reduction, (2) an embedding-dimension-adaptable CIM array mapping for truly parallel multi-head computation, and (3) a multi-ping-pong CIM macro with rescheduled attention-head dataflow to enhance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.05 \times$</tex> inference-level area efficiency. Implemented in 28-nm CMOS process, the proposed accelerator consumes <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$24.62 \mu ~\mathrm{J} /$</tex> token and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.03 \text{inference} / \text{mm}^{2}$</tex> for BERT-base, realizing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.12 \times$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.03 \times$</tex> energy and area efficiency improvements over state-of-the-art works.

In this paper, we present a five-layer polymer-based interposer technology using inkjet printing to fabricate silver vertical through-substrate vias (TSVs) for beyond 5G and edge-AI applications. Photosensitive epoxy resin (PESP) and polyimide (PSPI) are employed as low-loss dielectric materials, providing excellent thermal and mechanical stability. High-frequency measurements of microstrip line structures demonstrate good performance, with characteristic impedance close to 50 Ω and low insertion loss at 94 GHz. In addition, strong agreement between measurement and simulation results of a 79 GHz substrate-integrated waveguide (SIW) antenna confirms the feasibility of the proposed design. Compared with conventional interposer technologies, this approach offers a lightweight, low-cost, and high-performance solution for advanced heterogeneous integration, particularly in edge-AI sensing and high-frequency communication systems.

In this brief, we propose a first system chip architecture of 4-splitting tree-structure-based K-means clustering trainer and classifier. It mainly aims to efficiently detect cybersecurity attacks in the emerging AI-driven world. In addition, we also propose three design techniques to elaborate our chip, featuring a low-latency property in both training and classification aspects. Our developed architecture is first validated with the Xilinx FPGA platform. Furthermore, it is implemented in ASIC and well-verified with five representative cybersecurity-related datasets. The total core area with TSMC 40nm low-Vt CMOS technology only occupies 0.44 um2, maximally operating at 434.78 MHz and possessing a maximum classification throughput of 3.48 GBps on chip. In comparison, the speed-up ratio of training and classification is up to 9.33 and 8.73 times, respectively, successfully delivering a low-latency characteristic.

Array processing systems for wideband communication and sensing applications are progressively using a growing number of analog/RF elements. These systems require multiple identical analog-to-digital converters (ADCs) in fine lithography systems-on-a-chip (SoCs) for digital processing. Thermal and area constraints lead to increasingly stringent requirements on the individual power consumption (hence efficiency), physical size (hence cost), of all the integrated functions, including the data converters. This paper introduces an interleaved 12b/16GS/s ADC, implemented in a 4nm FinFET process, which addresses power and area challenges by incorporating innovations at both architecture and circuit levels. The ADC consumes 570mW, including calibration, on-chip supply regulation, reference buffers etc., with a Schreier figure of merit (FoMs) of ~148dB at Nyquist and an area of 0.430mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. It achieves a small-signal (-30dBFS) noise spectral density of -155dBFS/Hz, non-harmonic spurs better than -68dBFS (for a -1dBFS input tone at 7.4GHz), and a high-frequency SFDR of ~58dBc (also -1dBFS input tone at 7.4GHz) limited by HD2 (-58dB) and HD3 (-64dB), advancing the state-of-the-art.

With the rapid development of positioning, localization, navigation, and self-driving car systems, the implementation of intelligent and robust localization systems for real-time location-based services (LBSs) has become increasingly attractive. This article presents high-performance positioning and tracking approaches characterized by a pipelined structure, high computational efficiency, flexibility, and real-time processing, implemented using field programmable gate arrays (FPGAs). In triangulation-based positioning approaches, estimated distance information is derived from communication signals and the path loss model, while vertical localization is achieved through the characteristics of barometric pressure (BP). After integrating positioning approaches with tracking methods and BP sensors, the results illustrate that the proposed localization algorithms closely estimate the trajectory of mobile devices. For FPGA-implemented algorithms, the proposed approaches effectively handle floating-point operations, reduce computing resource usage, and provide real-time processing capabilities, surpassing software-based designs and implementations. In terms of performance, the results demonstrate that the localization accuracy of the proposed hardware-based implementation is nearly identical to that of the software-based approach. Regarding vertical location accuracy, based on the proposed calibration approach, the BP value increases by 11.6 Pa for every one-meter decrease in altitude. To maintain floor-level accuracy over time despite atmospheric fluctuations, a real-time dynamic calibration mechanism using a fixed reference sensor is employed. In summary, the proposed localization algorithms, implemented with FPGAs and BP sensors, offer advantages such as lower circuit costs, higher processing efficiency, and reliable vertical location accuracy for real-time public safety LBS.

Although suffering from inter-carrier interference (ICI), the proposed method can accomplish the channel estimation for the orthogonal frequency division multiplexing (OFDM) systems in high-mobility wireless communication environments using the conventional equally-separated stand-alone pilot arrangements. Initially, rough channel estimation based on the pilots is used for decoding the multiple low-density parity-check (LDPC) codes in each OFDM symbol in the first iteration. Correct decoding results provide reliable decision feedback, and can be used to form pseudo pilots and be combined with the original pilots to enhance the channel estimation in the following iterations. Simulation results confirm that the proposed method can extend the applicability of the OFDM systems equipped with the conventional pilot arrangement in fast-fading channels.

Crystal oscillators (XO) are widely used in electronic systems, providing low-jitter and temperature-stable reference clock signals. The inherent frequency accuracy of XO is good of ± 10ppm within a range of $-40 \sim 80^{\circ} \mathrm{C}$. However, to have a better accuracy of $\lt \pm 5 \mathrm{ppm}$ for certain applications with harsh operating conditions (e.g. GPS and aerospace), a low-power temperature-compensated XO (TCXO) is desired.