MunEDA (Germany)

Chapter 4 presents various dedicated methods that support variability handling in the design process. Using these methods, the designer can analyze the effect of variations on his design and identify possible improvements.

This work presents novel analog sizing flows based on analytical techniques. A graph-based operating point driven sizing approach provides operating point voltages and a rough sizing with respect to constraints. A voltage-range analysis method using linearized operating-point models obtains information about feasible voltage ranges. A direct-sizing method solves nonlinear algebraic circuit equations directly to obtain design parameters from specifications. All three methods require no or only minimum simulation effort and can provide quick insight into circuit design space and constraints in an early design stage. They allow flexible inclusion into state-of-the-art simulation-based optimization flows, where they lead to improved results with less optimization effort and prevent unnecessary simulation effort on unfeasible circuit topologies. The sizing flows are enhanced by a commercial optimization tool in order to obtain reliable circuits.

Statistical analysis is generally seen as the next EDA technology for timing and power sign-off. Research into this field has seen significant activity started about five years ago. Recently, interest appears to have fallen off somewhat. Also, while a lot of focus has been put on research fundamentals, extremely few applications in industry have been reported so far. Therefore, a group including Infineon Technologies as a leading semiconductor IDM and various universities and research institutes, as well as an EDA provider has tackled key challenges to enable statistical design in industry in a publicly funded project called "Sigma65". Sigma65 strives to provide key foundations to allow a change from traditional deterministic design methods to future design methods driven by statistical considerations. The project starts with statistical modeling and optimization of library components and ranges to statistical techniques for designing ICs on gate level and higher levels. In this paper, we present some results of this project, demonstrating how the interaction between industrial perspective, research institutions and EDA provider enables solutions which are applicable already in the near future. After an overview of the industrial perspective of the current situation in dealing with variations recent results on both statistical timing and power analysis will be given. In addition, recent research advances on fast yield estimation concerning parametric timing yield will be given.

ABSTRACTThe degree of development of Spanish agriculture at the end of the XIX century and the beginning of XX is a controversial issue. In this respect the study of the integration of the domestic market could provide new evidence since the degree of the market integration can be considered an indicator of economic development. By using regional wheat prices this paper analyzes the Spanish market integration between 1891 and 1905. With this aim in mind we employ the usual cointegration approach as well as an alternative method based on spectral analysis that allows taking into consideration the existence of no synchronized cycles.

Summary form only given, as follows. The tutorial presents an introduction into "DfY/DfM - Design for Yield and Manufacturability" covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment. Intended audience: analogue- and mixed-signal circuit designers, CAD- and design-support engineers (library management, technology migration and design reuse, process characterisation)

We present a novel technique to automatically calculate an initial sizing of analog circuits that conforms to good design practice. The method is purely (DC) simulation-based and does not need symbolic design equations or user design knowledge. It identifies the space of feasible design parameters based on implicit specifications, which arise from the circuit topology. A sizing centered within this space is obtained by iteratively solving a maximum volume ellipsoid problem on approximations to the feasible parameter space. The result is well-suited as initial sizing because it safely satisfies all implicit specifications. Experimental results demonstrate the efficiency and reliability of our method.