DFY/DFM - design for yield and manufacturability (industrial tutorial)

Summary form only given. There is one universal truth in terms of design for manufacturing (DFM) - DFM tools and disciplines have always existed. In micron technologies, DFM methodologies were applied to ensure acceptable yield and adequate test coverage. However, nanometer technology has ushered in new and significant yield and manufacturing considerations and constraints. The lack of a major increase in yield improvement between the 350 nm and 180 nm nodes suggests that yield loss mechanisms are not only increasing, but they are increasing fast enough that 'cosmetic' improvements in tools and methodologies are largely offset. If EDA tools are to assist the semiconductor industry at the 90 nm and 65 nm nodes, there must be profound changes to existing tools, and the introduction of new technologies that allow designers to consider and optimize for manufacturing at each stage of the design, verification, tapeout and test process. Where will these new tools and capabilities appear? They will show up in all parts of the design flow, and also on the manufacturing floor. In particular, an immediate focus for the EDA industry must be to deliver new technology in four key areas: process modeling (electrical and lithographic); statistical analysis and visualization; design optimization; test and inspection.

The tools and techniques you need to break the analog design bottleneck! Ten years ago, analog seemed to be a dead-end technology. Today, System-on-Chip (SoC) designs are increasingly mixed-signal designs. With the advent of application-specific integrated circuits (ASIC) technologies that can integrate both analog and digital functions on a single chip, analog has become more crucial than ever to the design process. Today, designers are moving beyond hand-crafted, one-transistor-at-a-time methods. They are using new circuit and physical synthesis tools to design practical analog circuits; new modeling and analysis tools to allow rapid exploration of system level alternatives; and new simulation tools to provide accurate answers for analog circuit behaviors and interactions that were considered impossible to handle only a few years ago. To give circuit designers and CAD professionals a better understanding of the history and the current state of the art in the field, this volume collects in one place the essential set of analog CAD papers that form the foundation of today's new analog design automation tools. Areas covered are: Analog synthesis Symbolic analysis Analog layout Analog modeling and analysis Specialized analog simulation Circuit centering and yield optimization Circuit testing Computer-Aided Design of Analog Integrated Circuits and Systems is the cutting-edge reference that will be an invaluable resource for every semiconductor circuit designer and CAD professional who hopes to break the analog design bottleneck.

The mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have almost automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills, design cycle time. This paper presents a novel design flow for constrained optimization of nano-CMOS analog circuits. The proposed analog design flow combines polynomial-regression based models and genetic algorithm for fast optimization. For evaluating the effectiveness of the proposed design flow, power minimization in a 50nm CMOS based current-starved voltage-controlled oscillator (VCO) is carried out, while treating oscillation frequency as a performance constraint. Accurate polynomial-regression based models are developed for power and frequency of the VCO. The goodness-of-fit of the models is evaluated using SSE, RMSE and R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Using these models, we form a constrained optimization problem which is solved using genetic algorithm. The flow achieved 21.67% power savings, with a constraint of frequency ≥ 100 MHz. To the best of the authors' knowledge, this is the first study which approaches a VCO design problem as a mathematical constrained optimization involving the usage of regression based modeling and genetic algorithm.

Design for Manufacturability (DfM) improves semiconductor integrated circuit (IC) yield by optimizing product design or layout. Positive impact of DfM on yield can be realized at production time (e.g., parametric yield), at the end of production (e.g., functional yield), or in the field (e.g., reliability yield). Patents issued in 2007-2008 timeframe enhance DfM in all these domains. In this paper, we review examples of DfM patent coverage starting from the new correct-by-construction layout concepts for single cells, extending into multi-cell intellectual property (IP) and mask level. Another DfM patent family proposes new design verification techniques by which the manufacturing delivers feedback to design/layout e.g., to remove local yield limiters (hot spots). The new concepts involve EDA algorithms, computer programs, and design kits, which help optimize the DfM related modifications of the layout. A number of patents improve the way design or layout corrected by DfM is verified by inspection or simulation, before a mask set is built. They also address DfM data collection, storage, and transfer to improve communication and cross-fab compatibility, when the same mask set is delivered to different manufacturers or comes from different design houses, with important aspects of data protection and cost reduction.

BackgroundMost statistical design and analysis methods for clinical trials have been developed and evaluated where at least several hundreds of patients could be recruited. These methods may not be suitable to evaluate therapies if the sample size is unavoidably small, which is usually termed by small populations. The specific sample size cut off, where the standard methods fail, needs to be investigated. In this paper, the authors present their view on new developments for design and analysis of clinical trials in small population groups, where conventional statistical methods may be inappropriate, e.g., because of lack of power or poor adherence to asymptotic approximations due to sample size restrictions.MethodFollowing the EMA/CHMP guideline on clinical trials in small populations, we consider directions for new developments in the area of statistical methodology for design and analysis of small population clinical trials. We relate the findings to the research activities of three projects, Asterix, IDeAl, and InSPiRe, which have received funding since 2013 within the FP7-HEALTH-2013-INNOVATION-1 framework of the EU. As not all aspects of the wide research area of small population clinical trials can be addressed, we focus on areas where we feel advances are needed and feasible.ResultsThe general framework of the EMA/CHMP guideline on small population clinical trials stimulates a number of research areas. These serve as the basis for the three projects, Asterix, IDeAl, and InSPiRe, which use various approaches to develop new statistical methodology for design and analysis of small population clinical trials. Small population clinical trials refer to trials with a limited number of patients. Small populations may result form rare diseases or specific subtypes of more common diseases. New statistical methodology needs to be tailored to these specific situations.ConclusionThe main results from the three projects will constitute a useful toolbox for improved design and analysis of small population clinical trials. They address various challenges presented by the EMA/CHMP guideline as well as recent discussions about extrapolation. There is a need for involvement of the patients’ perspective in the planning and conduct of small population clinical trials for a successful therapy evaluation.

The article theoretically substantiates and develops a methodology for statistical assessment and analysis of the economic resilience of territories at the subnational level, taking into account the spatial coherence of multi-level development incentives, the construction algorithm of which is based on multi-level decomposition analysis in conditions of strictly determined spatial relations. The universal nature of the methodology allows it to be used in sectoral and regional (spatial) analysis.

This paper presents an integrated software environment that is used as part of a Design For Manufacturability (DFM) procedure. The software allows users to integrate simulation software with statistical analysis, incorporating Design Of Experiments (DOE) and contour plots. Techniques for investigating process variations are included allowing the process designer to choose the optimum processing conditions, and set realistic specifications on the process parameters.

Analog/Mixed-Signal (AMS) circuits present significant challenges to designers with the increase of design complexity and aggressive technology scaling. Design optimization techniques that account for process variation while presenting an accurate and fast design flow which can perform design optimization in reasonable time are still lacking. As a trade-off of the accuracy and speed, this paper presents a process-variation aware design flow for ultra-fast variability-aware optimization of nano-CMOS based physical design of analog circuits. It combines Kriging bootstrapped Neural Network (KBNN) metamodels with a Particle Swarm Optimization (PSO) algorithm in the design optimization flow. The KBNN provides a trade-off between analog-quality accuracy and scalability and can be effectively used for large and complex AMS circuits while capturing correlations in process variations. The effectiveness of the design flow is demonstrated using a 180nm CMOS based PLL as a case study with 21 design parameters. The KBNN metamodel is 24× faster than NN metamodeling.

In the growing regions across the globe, products are being differentiated not only by their performance but also on characteristics like noise, aesthetics, ergonomics, etc. Noise norms are getting more and more stringent and customers are looking for quieter products. Engineers and technicians now face the challenge of developing effective products for lower noise emissions in addition to enhanced performance. As generators are a major noise source in a power plant, it is essential to contain generator noise well within the limit to meet statutory requirements. The major contributors to generator noise include cooling fan, rotor jet, electromagnetic excitation and vibrations. These sources should be configured properly for reducing the overall noise. Therefore, it is essential to establish a robust process to predict the generator noise accurately. This paper describes the process for predicting generator noise by using Statistical Energy Analysis methodology. Correlation of the predictions with test data is also discussed.

This paper discusses an efficient statistical analysis methodology for system-level signal integrity analysis. In the proposed method, statistical variations of the design and operational parameters are mapped to system performance through simulations based on orthogonal Taguchi arrays. Using the sensitivity functions derived from these simulations, statistical distributions of the performance measures are computed. The sensitivity functions and probability distributions of the design parameters are utilized as a diagnosis tool to estimate the design parameters of a system for a given measured performance. The statistical methodology is applied for design space exploration to improve system performance. For demonstrating the concept, a source synchronous memory bus and a peripheral input-output (I/O) bus have been analyzed under design and operational variations.

Techniques for the design of robust low-voltage CMOS analog circuits are given. It is shown that both V/sub t/-independence and proper alignment between the input and output swings are crucial for effective design of low-voltage circuits.

The authors present some of the simulation tools available to IC technology and circuit designers and discuss their importance in a Design For Manufacturability (DFM) strategy. It is demonstrated how these simulators, when combined with Design Of Experiment (DOE) and Response Surface Methodology (RSM), can be used to increase engineering knowledge while at the same time reducing the number of simulations required to optimise a process. The idea of contour plotting response distribution parameters to help determine robust manufacturing conditions is also introduced together with a methodology of using simulation results to rapidly produce histograms of response distributions. An environment to help automate the above approach is presented, and its use as part of a DFM strategy is illustrated through an example of a process/device optimisation.

With increasing integration levels, more and more ICs and systems-on-chip turn into mixed-signal designs. Typical examples are telecom (Bluetooth, WLAN, xDSL...) and multimedia (digital video, MP3 audio...) systems. This hot topic session will explore the challenges that designers face with these mixed-signal designs, covering both technical and methodological challenges as well as engineering resource and skill shortage problems. On the technical side, basic challenges are in incorporating analog design in a digital-oriented system design flow, signal integrity problems (supply and substrate noise, crosstalk...), trailing analog design productivity and test. In addition, the session will discuss the emerging progress in the methodology and EDA field, ranging from new software startups to analog and mixedsignal IP providers. The session will start with a brief tutorial overview about the problems and emerging solutions in the mixedsignal domain, for the audience to get an update of the current state of the art in mixed-signal. This will be followed by a panel discussion, where the goal for the audience is to really explore where the unaddressed problems are in mixed-signal design and which problems are today close to being solved commercially in this dynamically moving market. Issues addressed by the panel members include the integration of analog and mixed-signal IP, the emergence of mixed-signal CAD tools including behavioral modeling and simulation as well as analog synthesis, the challenge of rapid technology changes and analog design retargeting, the mixed-signal signal integrity nightmare, the rise of specialized mixed-signal design companies, single-chip versus single-package integration, the trimming of analog courses in many recently restructured EE curricula and the shortage of analog designers. Proceedings of Design, Automation, and Test in Europe (DATE ’01) 1530-1591/01 $10.00 © 2001 IEEE

Since scaling of CMOS is reaching the nanometer area serious limitations enforce the introduction of novel materials, device architectures and device concepts. Multi-gate devices employing high-k gate dielectrics are considered as promising solution overcoming these scaling limitations of conventional planar bulk CMOS. Variation Aware Analog and Mixed-Signal Circuit Design in Emerging Multi-Gate CMOS Technologies provides a technology oriented assessment of analog and mixed-signal circuits in emerging high-k and multi-gate CMOS technologies.

Focusing in 2009 on Adaptive Circuits and Systems, ISSCC will offer four plenary talks, approximately 250 technical papers, nine evening panels and special evening sessions, all included in the registration price. Information about these events and the eight ISSCC 2009 circuit design forums, ten 90-minute tutorials, and an all-day Short Course on Low-Voltage Analog and Mixed-Signal CMOS Circuit Design will be published on the conference website in November.