Optimizing IC Design for Manufacturability

In integrated circuit (IC) design for advanced manufacturing processes, iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuits. Layout-dependent effects (LDEs) affect IC design and fabrication, resulting in differences in circuit functionality and performance in presimulation versus postsimulation. These differences can greatly increase the length of design iteration cycles. Foundries have attempted to accelerate the iterative design process by providing process design kit libraries to IC designers. However, these kits can neither fully mitigate the negative affect of LDEs on design for manufacturability (DFM) nor eliminate the difference between presimulation and postsimulation results. To address this problem, this study proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM parameters of all components in a circuit prior to the routing process; these parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components. Accordingly, the IC designer can determine the effects of DFM parameters on the circuit and modify them in advance if necessary. When the LDEs generated by device placement have been confirmed to not affect circuit properties, physical verification of the routing of metal wires in the IC layout can be performed. In this verification, postsimulations only need to focus on problems regarding the wire loading and timing effects of metal routing. The proposed design process is useful for mitigating LDEs in IC design and considerably reduces the time required for iterative improvement processes. Specifically, this study provides a method of enhancing design iteration cycles and provides guidelines for analyzing factors that hinder IC device functionality and performance. In sum, various problems can be resolved by separately extracting the DFM parameters associated with LDEs and parasitic parameters associated with routing.

The design for manufacturability (DFM) method is most effective when integrated with the new product development (NPD) process. Due to the focused nature of the associated product and process knowledge and the extensive effort required, there are many NPD situations where classical DFM techniques cannot be readily applied. In this paper, Pro-DFM a multi-criteria model for manufacturability analysis that identifies product realisation opportunities (PRO) for cost reduction is presented. The key assumption in Pro-DFM is that the NPD team has a baseline estimate of production costs, and the evaluation question is how DFM issues will affect the expected unit production cost. The Pro-DFM model analyses a new design in three different factors: part procurement and handling, product assembly fabrication processes, and inventory costs. Each of these is independently analysed using a hierarchy of multiple criteria and sub-criteria. This approach is found to be amenable to most NPD processes, and conducive to easy integration. Each evaluation sub-criterion is presented in the form of a simple query, which is associated with a set of responses that is flexibly anchored to a uni-dimensional scale. A case study example is used to demonstrate the DFM evaluation process and the derivation of the cost penalties.

Time and cost reduction during product development is important to meet the competitiveness in the market. Design for Manufacture and Assembly (DFMA) plays a key role in product development, especially in industries like aerospace, wherein variety in component geometry is more. Parts count reduction is one of the basic principles of DFMA. Design for Manufacture (DFM) considerations lead to simplification and standardization of design and manufacturing processes. It also facilitates integration of function and form and optimizes the workflow. This paper outlines the DFMA considerations to sheet metal parts considering factors such as standardization of geometric shapes and integral part design through parts count reduction. A methodology for integration of parts is presented, which is partly interactive, to evolve an integral design from a multipart sub-assembly. The method proposed is applied to a sheet metal parts sub-assembly, and it also compares the time and cost of manufacture and assembly.

Design for manufacturability (DFM) is inevitable because of the formidable challenges encountered in nano-scale integrated circuit (IC) manufacturing. Unfortunately, it is difficult for designers to understand the cost-benefit tradeoff when tuning their design through DFM to achieve better manufacturability. This work attempts to assist the designer in this aspect by providing a methodology (called RADAR --- Rule Assessment of Defect-Affected Regions) which uses failing-IC diagnosis results to systematically evaluate the effectiveness of DFM rules. RADAR is applied to the fail data from a 90nm Nvidia graphics processing unit (GPU) to demonstrate its viability. Specifically, evaluation of the via-enclosure rules revealed that they are much more needed in metal layers 3--6 than the remaining layers.

Angle grinder use in grinding a product and for high performances application, like deburring in foundries and construction. Consequently, this study investigates about the sustainability design of angle grinder with integration of Design for Manufacturing and Assembly (DFMA) analysis. Design for Manufacturing and Assembly (DFMA) is a process that produce a good product which is minimize complexity and number of part that lead to time and cost reduction in development. Sustainability design means a design solution that are advantageous to both human and nature in a complete and combined way. Sustainability design in this research include the production and assembly part which is analysis using DFMA method. The design solutions are minimizing the part number and assembly time problem regardless the costs, materials issues and selection of manufacturing process. Using the DFE method combined with Boothroyd and Geoffrey DFMA principle, the analysis on angle grinder by using the 3D scanning method in drawing some part using the Catia software and the sustainability analysis using Solidwork software is done. The result for current product efficiency is 21.3% with 15.34 KgCO2, 2.10×10−2 KgPO4, 15.5 KgSO2, 1.95 MJ produce in producing one angle grinder. Through this study, expecting 25% of reduction in all criteria study.

This chapter describes the use of genetic algorithms with the concept of niching for the conceptual design of superconducting magnets for the Large Hadron Collider, LHC at CERN. The method provides the designer with a number of possible solutions which can then be further optimized for field quality and manufacturability. 1 The conceptual design phase A particularity of the conceptual design phase is the “fuzziness” of the objectives and constraints. The main objectives are a small content of unwanted field errors in the main dipole field, low sensitivity of the field quality to manufacturing errors, easy manufacturing, and possibility to tune the geometry after the pre-series manufacture of the magnets. The “fuzziness” in these objectives is due to the fact that it is difficult to mathematically formulate all objectives. The amount of unwanted multipoles is expressed by the coefficients of the Fourier series expansion of the radial field component in the aperture where in the assumed symmetric case only the odd bn (coefficients of the sine terms) are to be minimized. However, using goal programming methods the weight for the components showing different sensitivity has to be found in an iterative procedure, as the effects of the components have to be examined using beam tracking. As the electro-magnetic forces are enormous (about 4000 kN/m radially) the local force distribution in the coil collar structure has to be optimized. However, this requires computations of coupled electro-magnetic mechanical problems. Manufacturing considerations include ease of the coil winding and collaring, i.e. geometrical constraints on the pole angle. Setting too many geometrical constraints results in ill-conditioned optimization problems. Requirements concerning the protection of the superconducting coils include low inductance, and a small current density in the copper stabilizer at a quench. These requirements are partly contradictory as with fewer turns the operating current increases. The calculation of peak voltage and temperature in the coils during a quench therefore requires network analysis and heat propagation calculations. During manufacturing, systematic errors occur due to the applied tooling. After the pre-series construction of the magnets the coils have to be repositioned to compensate for these systematic errors. It will be impossible to change the topology of the coil which therefore has to have sufficient flexibility for adjustments.

DfM (Design-for-Manufacturability) has become staple requirement beyond 100 nm technology node for efficient generation of mask data, cost reduction, and optimal circuit performance. Layout pattern has to comply to many requirements pertaining to database structure and complexity, suitability for image enhancement by the optical proximity correction, and mask data pattern density and distribution over the image field. These requirements are of particular complexity for Systems-on-Chip (SoC). A number of macro-, meso-, and microscopic effects such as reticle macroloading, planarization dishing, and pattern bridging or breaking would compromise fab yield, device performance, or both. In order to determine the optimal set of DfM rules applicable to the particular designs, Return-on-Investment and Failure Mode and Effect Analysis (FMEA) are proposed.

Many of the design companies cannot afford owning and acquiring expensive foundries and hence, go fabless and outsource their design fabrication to foundries that are potentially untrustwrothy. This globalization of Integrated Circuit (IC) design flow has introduced security vulnerabilities. If a design is fabricated in a foundry that is outside the direct control of the (fabless) design house, reverse engineering, malicious circuit modification, and Intellectual Property (IP) piracy are possible. In this tutorial, we elaborate on these and similar hardware security threats by making connections to VLSI testing. We cover design-for-trust techniques, such as logic encryption, aging acceleration attacks, and statistical methods that help identify Trojan'ed and counterfeit ICs.

The increased complexity, extensive verification requirement, shortened time-to-market, and increased manufacturing and test costs have made fabless design houses adopt the horizontal business model where system-on-chips (SoCs) are shipped to outsourced semiconductor assembly and test facilities. However, such a model renders offshore facilities complete control over the manufacturing and test of integrated circuits (ICs), potentially enabling them to perform attacks like IC overproduction, intellectual property (IP) piracy, shipping defective chips into the supply chain, and stealing security assets (e.g., locking keys). In this paper, we propose a novel protocol called POCA, enabling the first power-on chip authentication during wafer sort to securely provision design assets inside the chip. Using POCA, the design house can authenticate the chips on the untrusted manufacturing/test floor and generate a shared secret key with the chip. This key is then utilized to encrypt the secret assets and securely provision them inside the chip after decryption. To the best of our knowledge, POCA is the first protocol that performs authentication at an untrusted foundry and ensures secure communication with the chip during the test. POCA has been implemented for ASIC and FPGA environments and is proven resistant to all possible attacks known to us as of today.

Logic locking is a protection technique for outsourced integrated circuit (IC) designs that thwarts IC piracy and IC counterfeiting by untrusted foundries. In this technique, the IC design house locks the correct functionality of the circuit using a key that is known only to the trusted entities in the design house. As the correct key values are provided by the design house after production, a malicious adversary in the foundry house will not be able to unlock overproduced or counterfeit ICs. In this paper, we mount linear approximation attacks and differential attacks on random logic locking (RLL), fault-analysis based logic locking (FLL), and strong logic locking (SLL) techniques. We present a formal approach to mount the linear approximation attack on multiple circuit partitions and thereafter combining the approximations to form the attack on a locked logic cone of the circuit. We present our results on ISCAS’85 benchmark circuits. In linear approximation attack, the combinatorial blocks are partitioned and expressed as linear expressions to derive a relation between the primary inputs and the primary outputs of the circuit. The attack aims to determine the linear approximation that has the highest probability of occurrence for the correct key input. In differential attacks, we could recover the embedded secret key in device with attack effort lesser than exhaustive search attack.

This paper gives an overview of research that is expanding the domain of design for manufacturing (DFM) into new and important areas. DFM and assembly is widely used in industry, especially in product design and development process. to meet customer needs, companies are struggling with competitive markets to produce low cost products with high quality and faster to market. It becomes an important concept as the best time to find cost reductions, at design stage, rather than during manufacturing. The paper concludes with some general guidelines that suggest how manufacturing firms can develop useful, effective DFM. Overall goal with the paper is to aid designers, manufacturers, process planners in the practical industries on the ground and researchers in the mentioned area of study.

Due to the trend of globalized semiconductor supply chain, integrated circuits (IC) and hardware intellectual property (IP) are prone to serious security threats such as reverse engineering and IP piracy. In addition to the post-fabrication authentication techniques (e.g., IP metering), various hardware hardening approaches have emerged to resist reverse engineering and IP piracy. This chapter reviews three representable security hardening approaches—camouflaging, logic encryption/locking, and design obfuscation—that are applied to ICs at layout, gate, and register transfer levels. Particularly, this chapter presents a dynamic state-deflection-based obfuscation method, which deflects the state transition from the original transition path to a black hole cluster if an invalid key is applied to the hardware IP. This obfuscation method can successfully thwart the reverse engineering attack that exploits the code analysis support from electronic design automation (EDA) tools. Furthermore, this chapter extends the idea of design obfuscation for two-dimensional IC to emerging three-dimensional (3D) IC design technology. The proposed method is based on the insertion of a Network-on-Chip (NoC)-based shielding plane between two commercial dies to build the secure 3D ICs without involvement of trustworthy foundries.

Summary form only given, as follows. The tutorial presents an introduction into "DfY/DfM - Design for Yield and Manufacturability" covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment. Intended audience: analogue- and mixed-signal circuit designers, CAD- and design-support engineers (library management, technology migration and design reuse, process characterisation)

Facility layout design for modular construction manufacturing: A comparison based on simulation and optimization

A product redesign strategy can effectively shorten design lead time and reduce the manufacturing cost of innovative development for the manufacturing industry to stay competitive. Identification of function components is the basis of product redesign. Existing practices to identify the critical component and customer requirements are considered while complaint and historical failure data, crucial for improving product reliability, are frequently ignored. The objective of the article is to develop an integrated framework of product redesign and innovation considering customer requirements and product failure modes. The novel framework integrates the design for manufacturing and assembly (DFMA) and design for reliability (DFR) approaches, as well as finite element analysis to address the cost reduction of product redesign at early-stage, reliability improvement, and higher customer satisfaction. The proposed integrated framework is validated using an example of an Indonesian SME’s cooking stove. The redesigned cooking stove showed substantial improvements with 5.46% cost reductions, 20.32% design efficiency, and an 52.81% safety factor.