NXP (Germany)

Abstrack: Battery-powered mobile devices require multiple power domains to supply appropriate voltage levels to various sub-modules. This paper introduces a single-stage triple-output (SSTO) hybrid DC-DC converter that provides two regulatable half-VIN switching outputs and a 2:1 switched-capacitor (SC) output. The proposed SSTO converter offers a cost-effective solution, requiring only a single flying capacitor ($\mathrm{C}_{\mathrm{F}}$) and six switches, while providing functionality comparable to a conventional system comprising two three-level converters and a $2: 1$ SC converter (Fig. 1). Furthermore, the SSTO converter addresses the limitations commonly observed in SIMO converters [1–4]. It simultaneously delivers power to all three outputs while maintaining a constant switching frequency operation, even under significant load current (lload) imbalances. This enables high output power and low Vout ripple. In addition, reverse charge from lightly loaded or unloaded outputs is autonomously recycled to other outputs, thereby improving efficiency even under unbalanced Iload conditions.

Automotive Radar sensing technology is an essential component of modern passenger car Advanced Driver Assistance Systems (ADAS). Technical criteria such as sensor footprint, power consumption, safety and cost are subject to continuous development, optimization, and research. Specifically, the increasing complexity of a Radar System on Chip (SoC) poses significant challenges for the validation at system level during iterative hardware/software (HW/SW) co-development cycles. To address these challenges, this paper describes a novel test method for Radar SoC HW/SW variants, encompassing a tailored test case database, an advanced RF test platform and a modular test automation software framework. Selected test cases and test results for a Radar sensor reference design are shared to illustrate the test method’s effectiveness in achieving optimum test coverage of SoC functionality and system performance.

This paper investigates the impact of the input resistor thermal noise in high-resolution hybrid continuous-time/discrete-time (CT-DT) $\Sigma \Delta$ analog-to-digital converters (ADCs), with particular emphasis on the co-design of the input buffer and the ADC front-end. Targeting Industry 4.0 sensor interface applications, where accuracy and power efficiency are critical, this work addresses how the thermal noise originating in the CT stage limits the system signal-to-noise-ratio (SNR). A modeling strategy for this noise contribution is introduced and validated through Simulink ${ }^{\circledR}$ simulations, using a colored-noise approach, enabling a realistic spectral representation and accurate performance prediction. The proposed architecture, a thirdorder hybrid cascade-of-integrators-with-feedforward (CIFF) $\Sigma \Delta$ modulator, demonstrates compelling trade-offs between resolution, power consumption, and area. The adopted design choices are guided by analytical insights into integrator gain, RC time constants, and their effect on SNR performance. Simulation results confirm the effectiveness of the proposed approach, showcasing a $111.7-\mathrm{dB}$ SNR with a $0.8-\mathrm{V}$ input signal, at a $10.24-\mathrm{MHz}$ sampling frequency.

Advanced chips, built on innovative process nodes, are more susceptible to defects during manufacturing, making early detection critical. This necessity has driven the demand for extensive structural scan testing to screen for defects in the digital logic of System-on-Chips. The widely adopted Stuck-At (SA) and Transition-Delay (TD) scan ATPG fault models are not sufficient for screening out the defective parts and achieving low DPPM automotive parts. Targeted pattern generation for the SA and TD fault models is done only using port-level faults. Hence, the cell internal defects are not always visible via SA and TD patterns. The more recently developed Cell-Aware (CA) fault model has been successfully proven to be able to screen out the cell-internal defects. However, this approach incurs significant overhead, including CA-UDFM (user-defined fault model) generation. In this work, we present CTFM (CMOS Transition Fault Model), which uses custom UDFM files that target cell internal faults at the transistor level with less overhead compared with CA patterns. This is crucial for legacy designs, where fewer resources are typically allocated, especially compared to New Product Introduction (NPI) designs. A custom in-house diagnosis flow using our UDFM to improve scan diagnosis quality is also presented in this work.

Statistical verification is crucial for high-quality circuits in the presence of variations. To reduce the computational effort for large-scale circuits, individual subblocks are often abstracted by behavioral models. The computational cost to build and evaluate these models, as well as their accuracy in predicting the behavior of the physical circuit, depends strongly on the number of statistical parameters that are considered. To cope with this problem, we propose an approach to minimize the number of parameters without sacrificing statistical accuracy and inter-block correlations. To this end, we perform feature selection based on Spearman correlation in combination with the DBSCAN algorithm.

The reduction of LDL cholesterol lowers the risk of coronary and cerebrovascular events in individuals without manifest cardiovascular diseases. In Germany, statins at the expense of statutory health insurance had only been permitted for patients with atherosclerosis-related diseases or those at high cardiovascular risk (over 20 percent event probability within the next 10years, calculated using one of the "available risk calculators"). However, international guidelines recommend lower risk thresholds for the use of statins. The health and economic impacts of different risk thresholds for statin use in primary prevention within the German population are estimated for thresholds of 7.5, 10, and 15 percent over 10years, based on the US Pooled Cohort Equation (PCE) which is valid for Germany, using Markov models. Cost-effectiveness increases with a rising risk threshold, while individual benefit decreases with age at the start of treatment. The use of statins at a risk of 7.5 percent or more is cost-effective at any age (cost per QALY between 410 and 2100 Euros). In none of the examined scenarios does the proportion of the population qualifying for statin therapy exceed 25 percent. Lowering the threshold for statin therapy to a risk of 7.5 percent of either non-fatal myocardial infarction, coronary heart disease death, non-fatal or fatal stroke would align statin prescription in Germany with international standards. There is no urgent rationale for applying age-stratified risk thresholds.

The optimization of neural networks software and hardware techniques has enabled the integration of complex networks onto small devices, giving rise to the TinyML paradigm. This study focuses on applying TinyML to the recognition of beehive states, treating it as an audio event detection problem. Identifying crucial audio features for hive events, we present a machine learning pipeline covering model training, multi-stage evaluation, and conversion for deployment on the Arduino Nano BLE Sense 33. Achieving up to 99% accuracy, our approach facilitates early detection of anomalous behaviors in beehives, crucial for wildlife preservation. Automation in hyperparameter tuning, particularly in audio-related challenges, enhances efficiency in feature extraction, showcasing the potential of TinyML in solving realworld problems with minimal resources and power consumption.

Complex requirement for automotive accelerometer sensors new product development requires continuous innovation in QFN Cu wire bonding process. In this paper, an innovative thorough method to develop wire loop height and loop shape was developed to meet small QFN with package size 3x3mm with >40% dual die stack height increase vs. conventional product. Long wire length in terms of x, y, z direction has been studied on various loop type including forward and reverse bonding. The result of this study showed an optimized wire loop recipe can be achieved with zero wire short versus less optimized version which can cause as high as 36% wire short. The optimized wire loop recipe has been established and validated by T0 post mold test thus enabling a robust assembly process for small QFN sensor packages with significantly higher stacked die height.