ON Semiconductor (China)

Abstract As a high-precision equipment for solid-phase crystallization, surface mount technology (SMT) machine, whose accuracy has an important impact on the packaging of semiconductor chips. Due to the ultra-high speed reciprocating characteristics of the SMT machine, thermal error (TE) is the main influence factor. To reduce influence of TE on machining accuracy of SMT machine, a TE modeling method based on zebra optimization algorithm optimized least squares support vector machine (ZOA-LSSVM) is proposed. To start with, Canopy clustering algorithm is used to perform "coarse" clustering on the collected temperature variables to give the number of clusters and the initial cluster center. K-means clustering algorithm is used to cluster temperatures based on results provided by Canopy. Using entropy, an indicator of cluster validity, selecting the temperature point with the highest entropy value from each group as the temperature-sensitivity point(TSP), which can reduce the correlation interference between temperature measurement points. Secondly, with selected TSP as the input, the least squares support vector machine (LSSVM) prediction model is constructed, where zebra optimization algorithm (ZOA) is introduced to optimize penalty parameter γ and kernel function σ, and ZOA-LSSVM TE prediction model is established. Finally, taking X-axis of SMT machine as the object, the measurement and verification experiments for the machine tool's linear axis were designed.

The IC failures induced by accidental dropping event of modern handheld electronic devices such as mobile phones may result from various failure modes such as cracking of package(PKG), solder joint, etc. Generally, the board level drop test is normally adopted to evaluate the IC failure risk instead of the set level drop test considering cost and efficiency. Recently, however, the chip crack/damage failure rate in board level drop is much lower than that of mobile set level free drop. In this paper, a comprehensive study was performed to investigate the dynamic response characteristics of drop test with a customized PCB board when subjected to board level drop test and set level free drop test. The board level drop test was carried out according to JEDEC standard using a drop test apparatus, and the set level free drop test was employed by using the free drop machine. Moreover, two Finite Element models with reference to board level drop and set level free fall drop tests were developed to simulate the actual drop test scenarios based on two simplified FEA methods (Input-G method and impact velocity method, respectively). The simulation data were compared with experimental outputs to identify the FE Models in terms of accuracy of the results extracted. The dynamic key parameters of typical locations in PCB were analyzed to characterize performance difference during two kinds of drops. The measured and simulated data of corresponding locations in set level drop are all larger than those of board level drop in terms of impact acceleration intensity and duration, the strain response and the simulated chip stress. Comparing with board level drop response, a greater acceleration impact would induce a greater strain response, subsequently, the stress subjecting to chip of IC package is greater during set level free drop. Thus, we can conclude that the impact effect of set level free drop is severer than that of board level drop from experiment and simulation results, this can give a good explanation for the fact that failure rate of board level drop is much lower than that of set level drop.

Highly stable threshold voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$({V}_{\text {TH}})$ </tex-math></inline-formula> characteristics are an essential reliability requirement for p -GaN/AlGaN/GaN high-electron-mobility transistors (p-GaN HEMTs) to withstand various gate bias stresses for power applications. In this work, we demonstrate high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> (3.0 V) p-GaN HEMTs with robust <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> stability by p -GaN gate engineering via Mg doping and activation. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> degradation rates of the resulting device under both pulsed- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}/{V}$ </tex-math></inline-formula> and bias temperature instability (BTI) stress conditions are less than 10% at high temperatures up to 150°, which is much lower than that of conventional Schottky-type p -GaN HEMTs (20%–30%). Such notable <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> characteristics are due to the impact ionization (I.I.)-dependent hole compensation under certain gate stress, which effectively alleviates the electron trapping effect and reduces positive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift. The I.I. occurring in the fully depleted p -GaN layer has been confirmed by both positive temperature-dependent gate breakdown characteristics and numerical simulations. Furthermore, shallow- and deep-level hole traps are identified in the gate-stack of high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> devices by performing the deep-level transient spectroscopy (DLTS) technique. Consequently, the trapping effect associated with hole traps may also alleviate the undesired electron-trapping-induced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift. These results provide a critical understanding of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> stability of the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> p -GaN HEMTs (HVT-HEMTs) and important design guidance for commercial device development.

In this work, based on the selective-area p-type doping of GaN via Mg-ion implantation, quasi-vertical GaN junction-barrier-Schottky (JBS) diode on sapphire substrate was demonstrated. By combining the benefits of PN diodes and SBDs, the JBS diode achieved a high voltage and current rating of 830 V/60 A, as well as zero-reverse recovery characteristics. Additionally, the continuously repetitive breakdown in the UIS tests and positive temperature coefficient of the breakdown voltage further revealed the rugged avalanche capability of these diodes, showing their great potential in low-cost, fast-switching and highly-reliable power electronics applications.

Because of the special p-i-n structure of the tunneling FET (TFET), many different composite transistors can be formed with careful device design by combining TFET with MOSFET. In this paper, we propose the special applications of TFET as memory devices. A novel capacitor-less DRAM cell based on floating junction gate (FJG) concept can be configured with TFET. In addition, several different memory cells containing TFET will be discussed.