The Comparison Study of Board Level Drop and Set Level Drop Performance

A recent trend in portable electronics application is towards the use of Land Grid Arrays (BGAs without balls). While the Land Grid Array (LGA) package, with solder joint height of only 2 to 3 mils, offers the advantage of reduced mounted height for the package, the primary driver for its usage is the potential improvement in board level bend and drop performance. However, because of the reduced solder joint height, it is also expected that the thermal cycle performance of this package would degrade substantially compared to a similar package with balls. This paper examines the effect of this “ball-less” package on the bend and thermal fatigue reliability. Board level reliability tests (bend and thermal cycle) as well as simulations were performed comparing the LGAs with their BGA counterparts.

The main objective of this study is to develop a stress-buffer-improved package that is subjected to a board level drop test under a specific-G impact level. In this regard, both the drop test experiment and the ANSYS/LS-DYNA simulations are carried out. Several studies have shown that the solder joints having the brittle intermetallic compound (IMC) layers within the wafer level chip scale packaging (WLCSP) are the weakest part. For the most part, this is due to the large relative motion occurring between the board and the chip. In addition, the stress buffer layer exhibiting a relatively large elongation which reduces the impact on the solder balls. Meanwhile, the novel stress-buffer-improve package's failure mode is different from the convention WLCSP structure which shifts to the trace damage of the chip side. The leading concern between the solder ball and trace damage is the critical region where failure occurred owing to the stress concentration effect. During the drop test experiment, the proposed stress-buffer-improved package is able to survive over 100 drops (most packages survived at above 200 drops). Hence, this drop performance very much surpasses the Joint Electron Device Engineering Council (JEDEC) criterion (drop number is 30 times). Nevertheless, the metal traces which are embedded in the stress buffer layer suffered relatively larger deformation. Generally, the stress concentration occurs at a single position, much like the trace/pad connecting junction in the analysis of detailed stress-buffer-improved package. Finally, the predict result in finite element (FE) analysis is similar to the broken metal trace's failure analysis in the drop test experiment.

There have been tremendous demands on portable electronic devices since last decade and board level drop performance has become one of the major concerns in microelectronic ball grid array (BGA) package. Most studies focused on material selection of solder joints to improve drop performance. However, the risk for early failure in drop impact reliability still exists because it is sensitive to several factors such as substrate supplier, reflow conditions, loading condition and aging. In this paper, mild aging effect on drop performance was investigated to reduce early failure risk for lead free solder joints. From this study, for the case of relatively poor performance and interface dominant failure mode, mild aging could improve initial drop life with brittle-to-ductile transition.

Board level temperature cycle and drop test reliability data was collected for 23 × 23 mm FCBGA packages. Two different bare die thicknesses, the effect of lidded configuration, and two different board thicknesses were evaluated as key design factors. Different package warpage shapes modulated by two different assembly process flows, two different ball attach reflow profiles and ball attach rework were evaluated as key package process parameters. Two temperature cycle conditions were applied including JESD22-A104D Condition G and Condition N. Drop-shock test was also performed under JESD22-B104C Condition A and Condition B. The data suggested that bare die thickness and lidded configuration had significant impact on both temperature cycle and drop test reliability while the process parameters studied did not have a statistically significant effect. Composite substrate and board mechanical properties were characterized. Finite element analysis was conducted to interpret temperature cycle solder ball failure location considering both peeling stress and inelastic strain energy density.

The Wafer Level Chip Scale Package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of portable consumer electronics, such as cell phones. Due to differential bending between the silicon die and the PCB and the large stiffness difference, board level drop/bend tests are widely accepted methods to evaluate damage in the parts when a handheld device is dropped by the consumer. Through an aggressive product development program which includes experiment and simulation Amkor has developed the next level of WLCSP (CSP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nlTM</sup> ), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. The common industrial qualification criterion is for the product to withstand at least 40 drops before first failure (FF) under the JEDEC drop test condition of 1500 G/0.5 ms. With optimal CSP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nl</sup> and PCB designs, recent test results show that a typical Amkor CSP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nl</sup> with a die size of 5.4 mm × 5.4 mm has a minimum failure-free life of over 1000 drops. For an enhanced CSP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nl</sup> design, first-failure life of 4860 drops. was recorded in actual drop testing. These excellent results imply that much larger die are possible for future CSP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nl</sup> products, opening the door for wider applications of WLCSP devices, e.g. in next-generation portable electronics with greater function integration.

To final product quality of mobile phones, key reliability requirements are drop, bend and thermal cycling. Especially in terms of IC-device, drop reliability is the most significant of the three, and also difficult to optimize since it is a dynamic phenomenon in high speed and drop reliability is influenced by 1) system-level factors, 2) board-level and 3) micro-level. In this paper, system-level is defined as phone-level drop, specifically simplified mono-block phone including multiple devices on PWB. System-level enables to evaluate various factors, drop height, drop directions, materials to drop on, phone weight and phone mechanics. Board-level indicates IC-package, PWB and solder joints connecting in between. The board-assembled PWB is fixed onto fixture at 2∼6 points. Drop direction is flat drop only. This paper defines micro level as more detailed model than board level. PWB is modeled as composite structure consisting of dielectric materials with orthotropic properties, copper layers and micro via. IC-package is modeled as well. System level drop shows significant differences in drop directions and also the interactions between drop direction and component location. Micro level simulation results are well-correlative with experimental in failure mode. This paper will discuss overview of 3 levels of drop modeling and will focus on micro level and system level analysis in conjunction with board level.

Correlation studies for component level ball impact shear test and board level drop test

Based on the JEDEC standard, the three-dimensional finite element model of board level VFBGA package components was established, and the reliability of low silver lead-free solder Sn0.3Ag0.7Cu under drop impact was observed. The results show that, the mechanical impact and bending of PCB caused by mechanical shock are the main reasons which induce the drop failure of solder joint in the drop impact conditions; it is not neglect to consider the strain rate and thermal effect of solders in numerical simulation; as for low silver lead-free solder Sn0.3Ag0.7Cu, the distribution of the maximum stress on the joints was observed in the interface of the solder joints at low temperature; compared with high silver solder, the stress around test plate side silver solder is greater than that around the side of the package, while high silver solder just the opposite; and the maximum stress of low silver lead-free solder is much lower than that of the high silver solder, which shows better resistance to drop.

An effort has been made in this study to evaluate the characteristics of solder joint failure by using a new high speed impact tester. Here, a more thorough understanding of the solder joint behavior is examined by characterizing the behavior with respect to varying temperature and impact profiles. This is done in an attempt to address solder joint failures in actual product that may be under operating temperatures and environments. Comparison between the high speed pendulum impact test and drop test was primarily made by evaluating the failure modes from these two tests. Energy absorbed by the solder in a single impact has been used to predict the reliability in a board level test. Also the effect of temperature on the reliability of solder interconnects and on the strain rate induced in the PCB during a drop test has been studied.

PCB drop test lifetime assessment based on simulations and cyclic bend tests

Efficient multi-level modeling technique for determining effective board drop reliability of PCB assembly

Good correlation has been established between high speed shearing of solder joint at component level and board level drop tests, endorsing high speed shearing as a viable quality assurance test for manufacturing and incoming inspection. The high speed shear characteristics of solder joints under different test conditions (shear speed, shear angle, and temperature) and aging conditions (multiple reflow, temperature humidity, and salt spray) have been evaluated. Preliminary S-N characteristic for SnPb/spl I.bar/OSP and SnAg/spl I.bar/OSP solder joints have been generated using high speed cyclic bends test. These could be devolved into a life prediction model for board level solder joints in product drop impact.

Volumetric miniaturization of semiconductors and associated packaging is one of the largest driving forces within the industry. Initially motivated by the demand for smaller, more efficient and feature rich mobile electronics, this design trend has evolved and expanded across numerous applications. One example of a device designed to minimize size and maximize performance is the package that houses what is currently believed to be the world’s smallest 64 bit microprocessor [1, 2]. The processor is designed for applications such as Internet of Things (IoT) gateways, portable entertainment platforms, high performance portable storage applications featuring mobile HDD and mobile storage for rechargeable devices. The package chosen for this processor is a molded plastic land grid array (PLGA) because the final mounted height is kept to a minimum while maintaining robustness and reliability requirements. The package itself is only 9.6 mm x 9.6 mm x 0.805 mm. This paper explores the packaging design, SMT assembly process, and board level reliability testing for this package. The results of these evaluations are discussed as well, including warpage versus reflow, board-level thermal cycling, JEDEC drop and IPC bend testing performance. All of the evaluations and testing performed to date indicates that the flip chip PLGA is a robust packaging solution that meets or exceed the requirements of its various intended applications.

The miniaturization of microchips is always driving force for revolution and innovation in the electronic industry. When the pitch of bumps is getting smaller and smaller the ball size has to be gradually reduced. However the reliability of smaller ball size is getting weaker and weaker, so some traditional methods such as capillary underfilling, corner bonding and edge bonding process have been being implemented in board level assembly process to enhance drop and thermal cycling performance. These traditional processes have been increasingly considered to be bottleneck for further miniaturization because the completion of these processes demands more space. So the interest of eliminating these processes has been increased. To meet this demand, YINCAE has developed solder joint encapsulant adhesives for ball bumping applications to enhance solder joint strength resulting in improving drop and thermal cycling performance to eliminate underfilling, edge bonding or corner bonding process in the board level assembly process. In this paper we will discuss the ball bumping process, the reliability such as strength of solder joints, drop test performance and thermal cycling performance.

Accompanying the increasing popularity of portable and handheld products, high reliability for board level drop test becomes a great concern for semiconductor and electronic product manufacturers. Meanwhile, for design purpose, a reliable impact life prediction model is also a must in estimating the performance of packages subjected to drop impact. In this study, a stress-buffer-enhanced package is proposed to meet the high drop test performance requirement. Both the drop test experiment and numerical simulation were performed. The experimental drop test results showed that a different failure mode, the broken metal trace at package side, was observed in the stress-buffer-enhanced package. Several drop test simulations were conducted to elucidate the mechanical behavior of the test board and packages during the blink of impact. Based on the simulation results, a metal trace impact life prediction model is then developed for the novel stress-buffer-enhanced package to forecast the number of drops. Unlike the thermal cycle test, the dynamic response of the drop impact is irregular and not cyclic. As such, the concept of cumulative damage is considered in the life prediction model. Several characteristics of the metal trace dynamic response, the cumulative fatigue life, the cumulative plastic strain, and the cumulative effective plastic deformation, were studied during the development of the life prediction model. The results showed that the cumulative plastic strain of the metal trace could accurately predict impact life.