Advanced Analysis of WLCSP Copper Interconnect Reliability under Board Level Drop Test

The main objective of this study is to develop a stress-buffer-improved package that is subjected to a board level drop test under a specific-G impact level. In this regard, both the drop test experiment and the ANSYS/LS-DYNA simulations are carried out. Several studies have shown that the solder joints having the brittle intermetallic compound (IMC) layers within the wafer level chip scale packaging (WLCSP) are the weakest part. For the most part, this is due to the large relative motion occurring between the board and the chip. In addition, the stress buffer layer exhibiting a relatively large elongation which reduces the impact on the solder balls. Meanwhile, the novel stress-buffer-improve package's failure mode is different from the convention WLCSP structure which shifts to the trace damage of the chip side. The leading concern between the solder ball and trace damage is the critical region where failure occurred owing to the stress concentration effect. During the drop test experiment, the proposed stress-buffer-improved package is able to survive over 100 drops (most packages survived at above 200 drops). Hence, this drop performance very much surpasses the Joint Electron Device Engineering Council (JEDEC) criterion (drop number is 30 times). Nevertheless, the metal traces which are embedded in the stress buffer layer suffered relatively larger deformation. Generally, the stress concentration occurs at a single position, much like the trace/pad connecting junction in the analysis of detailed stress-buffer-improved package. Finally, the predict result in finite element (FE) analysis is similar to the broken metal trace's failure analysis in the drop test experiment.

Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

A low-cost, highly reliable UFI (UBM-free integration) wafer level chip scale packaging (WLCSP) for high performance, large die (>100 mm2) with fine solder ball pitch (350 µm) and high I/O (>800) has been developed. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5x5 mm2 with ball pitch smaller than 350 µm. In this paper, we present the novel WLCSP designed with a stress-mitigation structure which can significantly enhance the reliability of the package and enables die size extension. By controlling the maximum strain location and optimizing the materials using the stress-mitigation structure, the chip warpage and the stress between Si and PCB can be effectively reduced to enhance both component and board-level reliabilities of the package. The UFI WLCSP passed all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution (t63), respectively. As a result, highly reliable packages with various die sizes, including 5.2x5.2, 7.2x7.2 and 10.3x10.3 mm2 and with both 400 and 350 µm ball pitches have been developed. The RDL within the package of UFI WLCSP can be utilized to form inductor structure which exhibits quality-factor nearly 50% higher than that of an on-chip inductor. Besides, in WLCSP process, die sawing typically causes delamination and cracking of packages which results in process failure in the WLCSP. The UFI unique structure consists of sidewall protection which is capable of preventing chipping and therefore effectively improves the process controls and the reliability margins. In addition, to fulfill the requirement of high I/O products and to enhance the design flexibility, we embedded multiple RDL in UFI WLCSP with die size of 10.3x10.3 mm2 and ball pitch of 350 µm, which provides a fan-in package solution with I/O >800. The large die UFI WLCSP has passed the component-level reliability tests of TCB1000, uHAST96 and HTS1000, and board-level reliability tests of TCG500 and drop tests.

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm 2 body size, 18×15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a -40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.

The methodology for reliability analysis on the flexible electronics needs to be studied, both in the aspects of simulation and experimental tests. There appears to be very little work in the open literature on the reliability analysis of flexible electronics. In this article, we discuss FEM simulation in mechanical reliability analysis for the design of polyimide based multi-layer flexible printed wire boards. The reliability of the solder joints used to mount packages onto the flexible board under thermal cycling and drop test has been examined. An approximate simulation based approach has been developed to predict the equivalent material property of the multi-layer flexible board. The histogram feature in Adobe Photoshop has been introduced to evaluate the Cu percentage in a signal layer according to the drawing of the signal layer. Simplified FEA model has been built and a number of basic deformation modes have been simulated to retrieve the equivalent material property of a multi-layer flexible board. This approach has been verified by experimental measurement. In addition, it has been pointed out that for a multi-layer flexible board, it is not appropriate to just use the values of volume percentage of the components in a board as the weighting factors to evaluate the equivalent material property parameters of the board. The thermomechanical analysis has been conducted based on the industrial standard formula for solder fatigue life prediction relevant to the conventional PWB and package assembly. The simulation results are compared with experimental test data. The failure mechanism predicted by simulation is consistent with that observed in experimental tests. However, the simulation results of the solder fatigue life are about 1.8 times the test data. Further study is needed on extending or adjusting the conventional formula for solder fatigue life prediction so that it could be used in the case of multi-layer flexible board. The submodeling technique has been used in LS-DYNA to conduct strain and stress analysis on the critical solder during the board level drop test. Simulation results show that the solder shall fail first at the interface to the PWB side during the drop test. The effect of the change of the board thickness on the reliability of the solder joints has been investigated. It has been shown that the thinner the board, the smaller the peak values of the Von Mise stress and peeling strain at both the package and PWB sides of the solder joint interfaces. In addition, the correlation of the peeling strain on the critical solder with the bending strain on PWB near the critical solder has been examined. It has been shown that for a specific PWB platform, the more the bending strain on the board, and the more the peeling strain on the solder during drop test. Based on this study, the solder and/or PWB reliability could be efficiently evaluated by the combination of simulation and experimental measurements. The methods discussed in this article shall be useful in conducting reliability analysis of a general multilayer flexible board.

PCB drop test lifetime assessment based on simulations and cyclic bend tests

Solder joint reliability (SJR) under drop impact is a big concern for hand-held device such as mobile phone and PDA. In the semiconductor industry, generally board level drop test is used to assess solder joint performance under drop impact. JEDEC published a standard on drop test which defines drop impact pulse and test board configuration, and thus when the standard is strictly followed SJR drop test carried out by different semiconductor component manufacturers can be compared. However when the JEDEC drop test board is used for package qualification, there are some limitations. Firstly, the JEDEC test board provided so many solder joint loading conditions which are sometimes not necessary because the main drop test indicator is the earliest drop test failure which is dominated by the worst loading condition. Secondly, so many loading conditions reduce the sample size of each loading condition when the data are statistically processed. Here we propose an alternative test board design with only one loading condition and sufficiently large sample size, which is more suitable for package qualification statistically. Except the board shape and size and package component layout, all other board design requirement strictly follows the JEDEC standard so that it can be easily implemented.

An effort has been made in this study to evaluate the characteristics of solder joint failure by using a new high speed impact tester. Here, a more thorough understanding of the solder joint behavior is examined by characterizing the behavior with respect to varying temperature and impact profiles. This is done in an attempt to address solder joint failures in actual product that may be under operating temperatures and environments. Comparison between the high speed pendulum impact test and drop test was primarily made by evaluating the failure modes from these two tests. Energy absorbed by the solder in a single impact has been used to predict the reliability in a board level test. Also the effect of temperature on the reliability of solder interconnects and on the strain rate induced in the PCB during a drop test has been studied.

Accompanying the increasing popularity of portable and handheld products, high reliability for board level drop test becomes a great concern for semiconductor and electronic product manufacturers. Meanwhile, for design purpose, a reliable impact life prediction model is also a must in estimating the performance of packages subjected to drop impact. In this study, a stress-buffer-enhanced package is proposed to meet the high drop test performance requirement. Both the drop test experiment and numerical simulation were performed. The experimental drop test results showed that a different failure mode, the broken metal trace at package side, was observed in the stress-buffer-enhanced package. Several drop test simulations were conducted to elucidate the mechanical behavior of the test board and packages during the blink of impact. Based on the simulation results, a metal trace impact life prediction model is then developed for the novel stress-buffer-enhanced package to forecast the number of drops. Unlike the thermal cycle test, the dynamic response of the drop impact is irregular and not cyclic. As such, the concept of cumulative damage is considered in the life prediction model. Several characteristics of the metal trace dynamic response, the cumulative fatigue life, the cumulative plastic strain, and the cumulative effective plastic deformation, were studied during the development of the life prediction model. The results showed that the cumulative plastic strain of the metal trace could accurately predict impact life.

Multiple impact characterization of wafer level packaging (WLP)

Reliability performance during drop impact is critical for electronic handheld devices. In this paper, a comprehensive study in efficiency and accuracy of multiple finite element modeling approaches and solution techniques for a wafer-level package (WLP) is presented. JEDEC specified test board is used for the model study. A direct acceleration input method is introduced. Two types of global finite element models for a typical WLP are studied: solder layer and solder bump models. Two different approaches, full implicit dynamics and mode superposition, are applied to solve the JEDEC board dynamic responses. Based on this study, the 8-node solid element with smeared solder layer model, and the full implicit dynamics with either input-G or direct acceleration method are recommend. This combination results in short solution time and produces accurate dynamic solutions for drop test board. It has been found that the fundamental natural frequency of a JEDEC board with WLP typically ranges from 200 to 250 Hz for a large range of array size. There is a large strain gradient close to the component edge for each package on the test board. Due to the rigidity of the silicon chip, the board strain at the center of each component on the opposite side of PCB does not reflect the local bending behaviors of the board. The center of the board between two components might be a stationary point, which does not capture the board bending. With the increase of the chip size, the board strain at edge of each component will increase. The board peak strain at the corner package (U1, U5, U11, and U15) has been found greater than that at the center package (U8), but the bending direction is opposite. The components U6 and U10 have lowest board strains among all components.

In this study, the board level reliability (BLR) performance of different copper (Cu) post wafer level package (WLP) structures without epoxy or molding encapsulation have been evaluated and compared to standard WLP. The Cu post WLP test vehicle has been performed on different stack up structures of 4.7 x 7.1 mm2 package size at 0.4 mm ball pitch. The Cu post bumps of test vehicles were manufactured through main-stream production technologies including standard ball drop and electro-plated lead free solder after Cu post completed. The Cu post WLP will enhance the risk of board level solder joint fatigue due to thick Cu post without encapsulation will increase bump site stress. The optimized design parameters of package stack up with low temperature cured polyimide are implemented to accommodate the increased stress. In this work, we also evaluated a novel Cu post WLP stack up structure for fast package cycle time and fine pitch application. The improved BLR performance of large die size Cu post WLP is demonstrated in this investigation. The failure modes analysis and Weibull failure statistics are presented for the BLR results and recommendations as to the preferred Cu post WLP structure are also included.

Wafer level chip scale packages (WLCSP) have been increasingly used in portable electronic products such as mobile phones. Solder bumps with redistribution layer (RDL) are typical interconnect technology for WLCSP applications. One of the major concerns in joint reliability is the failure by temperature cyclic stresses. In addition, in terms of heat tolerance or device yields, process temperature of RDL dielectric is limited around 200deg.C in some packaging applications. According to our board level reliability test for temperature cycle test (TCT), photosensitive polyimide (PI) which is 200deg.C curable material has lower fail rate than polybenzoxazole (PBO) by TCT. In this study, we compared the actual board level test and Finite Element Analysis (FEA) during temperature cycle test, and correlated the mechanical and fatigue properties of passivation layer material with TCT reliability.

A plastic chip-scale package (CSP) smaller than conventional packages has been developed and applied to ATM switching systems. The package uses a low-cost glass-epoxy substrate. As glass epoxy is widely used in the printed circuit boards (PCBs) of ATM switching systems, its use in the CSPs mounted on a PCB reduces the difference in thermal expansion between PCB and CSPs, thus lengthening CSP life. The power plane, ground plane, and thermal vias of the CSP are designed to offset the increased thermal resistance due to the CSP's smaller size. Simulation showed a thermal resistance for this CSP with copper layers and thermal vias of as much as 22% less than that of a CSP with no copper layers or thermal vias. A six-layer test board mounting four CSPs was used to simulate a sub-board for ATM switching systems. The thermal resistance of the two CSPs located downstream was about 10% higher than that of the two located upstream. Two CSPs were developed for two types of application-specific ICs: a bus interface controller (BIC) and a peripheral interface circuit (PIC). Both CSPs were 18 mm square with a 0.8 mm outer solder-ball pitch and 256 outer balls. These CSPs occupied areas about 87% and 68% smaller than those of a conventional pin grid array (PGA) and quad flat package (QFP) respectively. The junction temperature of both CSPs satisfied the thermal conditions. These high-performance CSPs are thus attractive for use in ATM switching systems.