Reliability analysis for the design of a multi-layer flexible board

Accompanying the increasing popularity of portable and handheld products, high reliability for board level drop test becomes a great concern for semiconductor and electronic product manufacturers. Meanwhile, for design purpose, a reliable impact life prediction model is also a must in estimating the performance of packages subjected to drop impact. In this study, a stress-buffer-enhanced package is proposed to meet the high drop test performance requirement. Both the drop test experiment and numerical simulation were performed. The experimental drop test results showed that a different failure mode, the broken metal trace at package side, was observed in the stress-buffer-enhanced package. Several drop test simulations were conducted to elucidate the mechanical behavior of the test board and packages during the blink of impact. Based on the simulation results, a metal trace impact life prediction model is then developed for the novel stress-buffer-enhanced package to forecast the number of drops. Unlike the thermal cycle test, the dynamic response of the drop impact is irregular and not cyclic. As such, the concept of cumulative damage is considered in the life prediction model. Several characteristics of the metal trace dynamic response, the cumulative fatigue life, the cumulative plastic strain, and the cumulative effective plastic deformation, were studied during the development of the life prediction model. The results showed that the cumulative plastic strain of the metal trace could accurately predict impact life.

The Wafer Level Chip Scale Package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of portable consumer electronics, such as cell phones. Due to differential bending between the silicon die and the PCB and the large stiffness difference, board level drop/bend tests are widely accepted methods to evaluate damage in the parts when a handheld device is dropped by the consumer. Through an aggressive product development program which includes experiment and simulation Amkor has developed the next level of WLCSP (CSP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nlTM</sup> ), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. The common industrial qualification criterion is for the product to withstand at least 40 drops before first failure (FF) under the JEDEC drop test condition of 1500 G/0.5 ms. With optimal CSP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nl</sup> and PCB designs, recent test results show that a typical Amkor CSP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nl</sup> with a die size of 5.4 mm × 5.4 mm has a minimum failure-free life of over 1000 drops. For an enhanced CSP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nl</sup> design, first-failure life of 4860 drops. was recorded in actual drop testing. These excellent results imply that much larger die are possible for future CSP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nl</sup> products, opening the door for wider applications of WLCSP devices, e.g. in next-generation portable electronics with greater function integration.

Solder joint reliability (SJR) under drop impact is a big concern for hand-held device such as mobile phone and PDA. In the semiconductor industry, generally board level drop test is used to assess solder joint performance under drop impact. JEDEC published a standard on drop test which defines drop impact pulse and test board configuration, and thus when the standard is strictly followed SJR drop test carried out by different semiconductor component manufacturers can be compared. However when the JEDEC drop test board is used for package qualification, there are some limitations. Firstly, the JEDEC test board provided so many solder joint loading conditions which are sometimes not necessary because the main drop test indicator is the earliest drop test failure which is dominated by the worst loading condition. Secondly, so many loading conditions reduce the sample size of each loading condition when the data are statistically processed. Here we propose an alternative test board design with only one loading condition and sufficiently large sample size, which is more suitable for package qualification statistically. Except the board shape and size and package component layout, all other board design requirement strictly follows the JEDEC standard so that it can be easily implemented.

Board-level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this study, drop test of printed circuit boards (PCBs) with a four-screw support condition was conducted for a 15 mm times 15 mm fine-pitch ball grid array (FBGA) package assembly with solder ball compositions of 36Pb-62Sn-2Ag and Sn-4Ag-0.5Cu on printed circuit board (PCB) surface finishes of organic solderability preservative, electroless nickel immersion gold, and immersion tin. Finite element modeling of the FBGA assembly was performed to study the stress-strain behavior of the solder joints during drop test. The drop test results revealed a strong influence of different intermetallic compound formation on soldered assemblies drop durability. The lead-based solder supersedes the lead-free composition regardless of the types of surface finish. Joints on organic solderability preservative were found to be strongest for each solder type. Other factors affecting drop reliability such as component location on the board and thermal cycling aging effects are reported. Finite element modeling results showed that a solder joint is more prone to failure on the PCB side, and the predicted solder joint stresses are location dependent. Predicted failure sites based on simulation results are consistent with experimental observations.

After the adoption of lead-free electronic products, the halogen-free electronic products are expected to increase in the coming years for environmental protection and green electronics. Currently, for evaluating the drop resistance of handheld electronic products, the board level drop test method is typically employed. In this study, the finite elements analysis was used to analyze the drop responses of totally halogen-free PCBA and the simulation results were verified by drop tests. The outer layers of the halogen-free test board were built-up by resin coated copper (RCC) material. According to the JESD22-B111 standard, five PBGA components with Sn-4Ag-0.5Cu solder balls were mounted on the test board by the Sn-1Ag-0.5Cu solder paste. The ANASYS software was employed to analyze the stress distribution in the joint structures which contained the solder ball, copper pad, and build-up material during drop impacts. The sub-modeling simulation method was used to improve the accuracy and convergence of the simulation results. In addition, by using the support excitation scheme, the contact moment in the impact process during the drop test was translated into effective support excitation loads to simplify the analysis. From the drop test results, failure analysis showed that most of the fractures occurred around the pad on the test board first and then cracks propagated across the outer build-up material. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. The simulation revealed that the maximum normal stress was located at the outmost solder balls in the PCB side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

The Sn–Bi solder paste is commonly used in electronic assembly and packaging, but its brittleness causes poor reliability in shock environments. In this study, the mechanical reliability of Sn–Bi solder paste and Sn–Bi composite solder paste with thermosetting epoxy (TSEP Sn–Bi) was investigated with the board level drop test. The crack characterizations of solder joints were evaluated using a stereomicroscope after the dye and pull test. The microstructure characterization and failure types of solder joints were analyzed by a scanning electron microscope (SEM), and an energy dispersive spectrometer (EDS) was employed to investigate the initial phase identification and elemental analysis. Compared with Sn–Bi solder paste, the results show that the TSEP Sn–Bi solder pastes reduced the proportion of the complete failure and partial failure of the solder joints during the drop test. The microstructure observation of the crack path showed that the Sn–Bi/TSEP Sn–Bi solder joints were reinforced through the cured epoxy resin. The number of drops of the Sn–Bi/TSEP Sn–Bi-x (x = 3, 5, 7) solder joints had 1.55, 2.57, and over 3.00 times that of Sn–Bi/Sn–Bi solder joints after the board level drop test.

A comprehensive analysis of delamination and thermoelectric performance of thermoelectric pn-junctions with temperature-dependent material properties

We propose an effective approach for designing a multi-lattice structure (MLS) that simultaneously considers local densities and the fillet-joint shape of struts to express practical equivalent material properties. The density of each cell is optimized by changing the strut diameter and fillet-joint radius according to loading conditions. The equivalent material properties of MLS, such as elastic modulus and shear modulus, are calculated based on a computational homogenization method. Finite element analyses of the full-shape and homogenized lattice model under external compressive load are conducted to evaluate the equivalent material properties. We also designed an optimized three-point bending structure using the proposed method. Based on the results of the topology optimization, three types of lattices with different relative densities are designed in a local zone considering local deformation modes. The result of this work shows that multi-lattice bending structure has about 86.9 % higher strength than that of a uniform BCC lattice structure with the same weight.

PCB drop test lifetime assessment based on simulations and cyclic bend tests

An effort has been made in this study to evaluate the characteristics of solder joint failure by using a new high speed impact tester. Here, a more thorough understanding of the solder joint behavior is examined by characterizing the behavior with respect to varying temperature and impact profiles. This is done in an attempt to address solder joint failures in actual product that may be under operating temperatures and environments. Comparison between the high speed pendulum impact test and drop test was primarily made by evaluating the failure modes from these two tests. Energy absorbed by the solder in a single impact has been used to predict the reliability in a board level test. Also the effect of temperature on the reliability of solder interconnects and on the strain rate induced in the PCB during a drop test has been studied.

The main objective of this study is to develop a stress-buffer-improved package that is subjected to a board level drop test under a specific-G impact level. In this regard, both the drop test experiment and the ANSYS/LS-DYNA simulations are carried out. Several studies have shown that the solder joints having the brittle intermetallic compound (IMC) layers within the wafer level chip scale packaging (WLCSP) are the weakest part. For the most part, this is due to the large relative motion occurring between the board and the chip. In addition, the stress buffer layer exhibiting a relatively large elongation which reduces the impact on the solder balls. Meanwhile, the novel stress-buffer-improve package's failure mode is different from the convention WLCSP structure which shifts to the trace damage of the chip side. The leading concern between the solder ball and trace damage is the critical region where failure occurred owing to the stress concentration effect. During the drop test experiment, the proposed stress-buffer-improved package is able to survive over 100 drops (most packages survived at above 200 drops). Hence, this drop performance very much surpasses the Joint Electron Device Engineering Council (JEDEC) criterion (drop number is 30 times). Nevertheless, the metal traces which are embedded in the stress buffer layer suffered relatively larger deformation. Generally, the stress concentration occurs at a single position, much like the trace/pad connecting junction in the analysis of detailed stress-buffer-improved package. Finally, the predict result in finite element (FE) analysis is similar to the broken metal trace's failure analysis in the drop test experiment.

Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

There are so many applications of perforated pates with various penetration patterns. If they are penetrated regularly, it can be represented by solid plate with equivalent material properties, which has a benefit of finite element modelling and reducing computation time for the analysis. Because the equivalent material properties suggested already are not proper to be applicable for the dynamic analysis, it is necessary to extract the equivalent material properties for the dynamic analysis. Therefore, in this study, the equivalent modulus of elasticity are obtained for the perforated plate with a triangular penetration pattern by comparing the natural frequencies of the perforated plate with those of solid plate, which are represented with respect to the ligament efficacy. Using the equivalent material properties suggested, the modal analyses of the partially perforated rectangular plate with a triangular penetration pattern are performed and its applicability is shown by comparing natural frequencies of perforated and homogeneous solid plates from finite element method and analytical method.

The ball impact test (BIT) is developed based on the demand of a package-level measure for the board-level drop reliability of solder joints in the sense that it leads to fracturing of solder joints around the intermetallics, similar to that from a board-level drop test. In this paper, both board-level drop test and package-level ball impact test are examined numerically for solder joints of different Sn-Ag-Cu compositions. We propose a stress-based drop reliability index that involves the strength of intermetallics and the maximum interfacial normal stress the solder joints have experienced during the drop impact process. Correlations between the drop reliability index and BIT characteristics are found to be dependent on solder compositions. However, the correlations appear to be universal, i.e., independent of solder compositions, when certain constant multipliers are introduced

Reliability and failure analysis of SAC 105 and SAC 1205N lead-free solder alloys during drop test events