Enhanced Design and Reliability Analysis of Copper Post Wafer Level Package

A low-cost, highly reliable UFI (UBM-free integration) wafer level chip scale packaging (WLCSP) for high performance, large die (>100 mm2) with fine solder ball pitch (350 µm) and high I/O (>800) has been developed. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5x5 mm2 with ball pitch smaller than 350 µm. In this paper, we present the novel WLCSP designed with a stress-mitigation structure which can significantly enhance the reliability of the package and enables die size extension. By controlling the maximum strain location and optimizing the materials using the stress-mitigation structure, the chip warpage and the stress between Si and PCB can be effectively reduced to enhance both component and board-level reliabilities of the package. The UFI WLCSP passed all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution (t63), respectively. As a result, highly reliable packages with various die sizes, including 5.2x5.2, 7.2x7.2 and 10.3x10.3 mm2 and with both 400 and 350 µm ball pitches have been developed. The RDL within the package of UFI WLCSP can be utilized to form inductor structure which exhibits quality-factor nearly 50% higher than that of an on-chip inductor. Besides, in WLCSP process, die sawing typically causes delamination and cracking of packages which results in process failure in the WLCSP. The UFI unique structure consists of sidewall protection which is capable of preventing chipping and therefore effectively improves the process controls and the reliability margins. In addition, to fulfill the requirement of high I/O products and to enhance the design flexibility, we embedded multiple RDL in UFI WLCSP with die size of 10.3x10.3 mm2 and ball pitch of 350 µm, which provides a fan-in package solution with I/O >800. The large die UFI WLCSP has passed the component-level reliability tests of TCB1000, uHAST96 and HTS1000, and board-level reliability tests of TCG500 and drop tests.

Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm 2 body size, 18×15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a -40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (<2.5mm), low pin counts (<25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is subject to the price-pressure that accompanies this transition. More recently, the semiconductor industry has seen advances in WLCSP technology which have enabled the qualification envelope to be expanded to products with pin counts > 120. These advances have facilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory, many of which require advanced silicon technology nodes as well. Consequently, WLCSP is expanding to markets and applications previously supported by QFN and flip chip CSP. This expansion puts additional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is further enhanced by the changing business models and supply chain strategies adopted by companies in the new economic environment. To meet these growing market demands, WLCSP providers are faced with the challenges of providing faster cycle times and higher capacity without significant increases in capital expenditure. The above factors have driven the need for new WLCSP technologies that utilize fewer process steps compared to common WLCSP product offerings, while maintaining the robustness necessary for meeting quality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to cater to the cost and performance requirements of the diverse application space. This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows. This paper will examine material options, i.e., polymers and solder alloys, for these new structures and will also examine the effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modes produced during reliability testing will be coupled with mechanical simulations to enhance understanding of the failure mechanisms and to further strategies for improving product reliability.

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Chip-scale package (CSP) is commonly seen on high density boards as it minimizes the foot print while packed more functionality into one component. Board level reliability concern over CSPs is that finer pitch limits the solder ball size attached and the stencil thickness used in assembly which leads to much smaller joint volume and standoff while larger die-to-package ratio typically means higher stress level caused by the CTE mismatch. Prior studies have shown that the grain orientation may impact SnAgCu solder joint reliability. With less solder volume, the joint reliability of fine pitch SnAgCu solder may be more sensitive to the grain size, grain orientation, and IMC formation within the bulk solder. The purpose of the study is to evaluate the board level reliability of Pb-free ball grid array (BGA) packages with ball pitch smaller than 0.5mm under different packaging and assembly conditions. Based on a test vehicle with 0.4mm pitch daisy-chained CVBGA, the impact on solder joint reliability from a wide spectrum of variables such as PCB thickness, SMT configuration, die size, package pad finish, and mini cycle profiling has been investigated. The results of this study enable us to better understand the Pb-free fine pitch joint behaviors under different conditions and the factors that have significant impact on joint reliability. Isothermal aging effect has also been studied, will be presented in a separated paper, which demonstrated that isothermal aging could significantly degrade joint reliability for fine pitch packages. The ATC results proved that the fine pitch packages may underperform the components with regular 0.8-1.0mm pitch therefore extra attention needs to be paid on fine pitch components while converting high reliability products to Pb-free.

Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm2 body size, 18x15 BGA array, 0.5 mm pitch) will be presented. It will be demonstrated how extensive design enhancements, predictive simulations, careful package materials and process selection and assembly process optimization studies are required to develop a robust package solution. Multiple assembly process experiments and corner studies were conducted to demonstrate robustness of WLCSP package solution to meet automotive grade quality and reliability requirements. Both component/unit level and board level reliability was evaluated as per AECQ100 standards. Robustness margins were confirmed through reliability testing performed up to 2-3x reliability requirements.

Current industry trends in the microelectronics packaging is going towards increasing in I/O density and small size packaging. Common use of solder material in packaging are the lead free solders. The popular lead free alloys include the SnAgCu (SAC) family such as SAC 305 and SC405. SAC solder alloys are favor due to high stains rate transient load and reliable operation at high temperature. Hence, it is suitable for application such as military application, avionics, and automotive [1], [2]. SAC alloy is frequently used in Wafer Level Chip Scale Package designs but achieving board level reliability especially when footprint go beyond a certain size causes challenge for SAC solder ball [3]. To overcome this issues, new type of solder alloy, SACQ and QSAC, has been established in current market to improve board level reliability performance. In this paper, studies of the 2nd level solder joint of the SAC305, SAC-Q and QSAC solder ball in terms of ball shear strength measurement at time zero and its failure mode will be shared. The SAC305, SACQ and QSAC solder alloys are also subjected to High Temperature storage (HTS) at 150°C for up to 1000hrs. The different IMC layers and the IMC growth will be investigated in this work. In this paper, studies of the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> level solder joint of the SAC305, SAC-Q and QSAC solder ball in terms of ball shear strength measurement at time zero and its failure mode will be shared. The SAC305, SACQ and QSAC solder alloys are also subjected to High Temperature storage (HTS) at 150°C for up to 1000hrs. The different IMC layers and the IMC growth will be investigated in this work.

The system-in-package (SiP) is widely used in communication device that integrated multi components and packages into one system. However, the board level reliability performance becomes more important, especially cyclic bending test. In the work, both experimental and numerical model are performed to investigate the four point cyclic bending test with different load displacement. The bending test experiment was analyzed by Weibull method to calculate the solder fatigue life of SiP module. A three-dimension finite element method (FEM) and the Anand's visco-plasticity Model are used to simulate solder's creep behavior under cyclic bending test. It was constructed and experimentally benchmarked to qualitatively figure out solder joint failure location in whole package and crack position in solder interconnection. Besides, the constructive index, plastic work density (PWD) accumulated per cycle, is used to evaluate the risk of solder fatigue cracking failure and be correlated well from experimental characteristic cycles. This work provides design guideline for SiP module board level reliability under bending test. The factors that underfill dispensing effect and material type suggestion are also considered in this work.

The fan-out-type chip scale package (fan-out CSP) is an embedded chip packaging technology that eliminates the need for wirebonds and flip-chip bumps. In this study, the board-level reliability of fan-out CSP is studied by using three-dimensional finite element analysis. A design of simulations study is applied to investigate the influences of package geometry on the board-level interconnect reliability of fan-out CSP. Results of the analysis indicate that better board-level reliability for the fan-out CSP can be achieved by using a thicker die with thinner molding compound. In addition, the response surface model obtained from the design of simulations study can be served as the basis for further fan-out CSP design optimization.

Developing a CSP at waferlevel is a challenging task with respect to board level reliability. Board level reliability should be achieved in contrast to flip chip technology without underfilling. Of course the target of a CSP manufacturing technology at waferlevel is cost reduction. The S/sup 3/-Diepack is a waferlevel CSP developed at the Technical University of Berlin within the European ESPRIT project ESCHETA. The S/sup 3/-Diepack uses a redistribution layer to a achieve a standardized I/O-array and stacked solder spheres with a solder support structure (S/sup 3/) to improve board level reliability. The S/sup 3/-Diepack used in this investigation has a size of 10 mm/spl times/10 mm, 196 I/O's and a pitch of 0.5 mm. Due to the stacked solder spheres a stand-off height of about 0.4 mm is achieved after assembly. 1000 cycles -40 to +100/spl deg/C have been achieved on a thin FR5 board before electrical failure. Over 750 cycles -55 to +125/spl deg/C were passed on thick FR4 board.

Second level interconnect (SLI) or board level reliability (BLR) solder joint fatigue has been investigated extensively by OEM, ODM and OSAT. The influencing factors are well understood that package form factor (FF) and BGA pattern are primary factors. Modeling and testing correlate well in identifying failure location and predicting fatigue life. Previously bump level (FLI) is less touched due to large pitch and less fatigue reliability concerns. With the technology shift to more Chip Scale Package (CSP) FF and finer bump pitch, bump fatigue failure frequently occurs and meeting the reliability requirement become more challenging. However, even bump fatigue becomes more prominent, still not enough effort has been invested due to the modeling complexity when UF is present. As the first step towards developing bump fatigue life prediction, we carried out parametric finite element analysis (FEA) and investigated the factors from material, packaging design aspects that are often neglected in BLR. FEA study showed that with the presence of underfill, more factors than SLI/BLR influence the bump fatigue failure prediction. Key parameters that could affect failure location and life prediction are presented here.

Wafer Level Chip Scale packages use packaging technology at the wafer level instead of traditional method of assembling individual devices in packages. WCSP boards are being extensively used in handheld devices due to its smaller form factor, low cost and high packaging efficiency. WCSP has a relatively short solder life compared to other packages and so the reliability of these packages are of great concern. A PCB is a multi-layered structure in which each layer has different material characteristics and has a significant effect on the board itself. Removal of layers or changing the composition of the layers affects the solder balls' life [1], thus impacting the solder joint reliability of the boards. One of the key parameters in board level reliability is thermal cycling and during thermal cycling, stress is accumulated in the solders due to warpage of the board caused by coefficient of thermal expansion (CTE) and modulus mismatch between the layers [2-3]. This paper will try to address the possible effect of individual layers during thermal cycling by considering layer removal and by considering boards with different thickness created.

In the last decade, the Ultra-Thin HDI (High Density Interconnect) technology has dominated the mobile/wearable products designs, yet the standard test vehicles used for qualifying materials, components and connectors provided by IPC (Institute of Printed Circuits), ANSI (American National Standard Institute) and JEDEC (Joint Electron Device Engineering Council aka Solid State Technology Association), are obsolete and OEM’s (Original Equipment Manufacturer) have stopped using them. These test vehicles do not reflect the form factors, density and interconnect methods used by the industry. In addition, they do not capture failure modes of the fine pitch BGA (Ball Grid Array) technology and as a result don’t provide upstream Users adequate data for development. Microvias and dielectrics are the key, along with finer lines and spaces, in obtaining the density of Ultra-Thin HDI boards. Continuous reduction in PCB dimensions and feature sizes challenges both fabrication process and test vehicles. HDP User Group’s paper gives a brief introduction to the modern Ultra-Thin PCB (Printed Circuit Board) fabrication process. It discusses typical board level reliability tests and presents a generic reliability test vehicle design which is based on current Ultra-Thin HDI technology. With the proposed test vehicles’ design of modularity and scalability it is easy to modify to meet the next generation of Ultra-Thin HDI PCB requirements. The study indicates that the proposed TV design covers HDI test requirements and most of the current tests are critical when evaluating modern Ultra-Thin HDI circuit board reliability. The HDP User Group project also conducted a study on the application and reliability of a very fine pitch WLCSP (Wafer Level Chip Scale Package) on this Ultra-Thin HDI test vehicle. A 0.3mm pitch WLCSP daisy chain, commercially available solder paste, flux and underfill were used for this study. The details of the assembly process including solder paste printing, dip flux, component placement, reflow and underfill dispensing are discussed. The impact of the test vehicle OSP (Organic Surface Protection) surface finish on the assembly process and result is addressed as well. JEDEC standard air-to-air thermal cycling and drop tests are performed for reliability evaluation purposes. The reliability data of solder paste printing vs. dip flux, underfill vs. non-underfill are compared and evaluated. All results show that the WLCSP application process and materials on the ultra-thin test vehicle are robust and reliable.

Wafer Level Chip Scale Package (WLCSP) technologies are being used more often in electronic components due to their smaller size and lower cost, and are being applied to larger die and ball matrix sizes. Originally implemented mainly in mobile devices (i.e., smartphones), WLCSP components are now frequently used in new product categories that have more stringent use conditions than the mobile space. The harsher use conditions raise a concern of solder joint reliability, especially in temperature cycling due to the difference in the coefficient of thermal expansion between the silicon die and the laminate motherboard. While cycle life can be extended by using underfill, underfilling makes the surface mount assembly process more complex and costly, increases cycle time and inhibits rework. To solve the challenge of extending cyclic life without underfill, new WLCSP structures and materials have been proposed. This paper describes the investigation of some of these innovative solutions through motherboard assembly and board level reliability testing. The package variables consisted of two WLCSP structures utilizing ball support mechanisms and a Bismuth (Bi) bearing solder ball that is expected to increase fatigue life. Packages were produced separately with each variable, along with legs that included both new packages and new alloy. The finished assemblies, along with a control leg of standard structure/solder, were subjected to drop testing and temperature cycling. Solder joint integrity was monitored in-situ to accurately identify duration to failure for Weibull analysis. The results clearly show that this new generation of WLCSP structures can offer dramatically improved fatigue life without a significant sacrifice in drop reliability. This benefit should allow the use of WLCSPs in more challenging environments, as well as providing designers the option of using larger package sizes in existing mobile designs.

Multiple impact characterization of wafer level packaging (WLP)