Board Level Reliability Study of Next Generation Large Die Wafer Level Chip Scale Package Structures

A low-cost, highly reliable UFI (UBM-free integration) wafer level chip scale packaging (WLCSP) for high performance, large die (>100 mm2) with fine solder ball pitch (350 µm) and high I/O (>800) has been developed. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5x5 mm2 with ball pitch smaller than 350 µm. In this paper, we present the novel WLCSP designed with a stress-mitigation structure which can significantly enhance the reliability of the package and enables die size extension. By controlling the maximum strain location and optimizing the materials using the stress-mitigation structure, the chip warpage and the stress between Si and PCB can be effectively reduced to enhance both component and board-level reliabilities of the package. The UFI WLCSP passed all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution (t63), respectively. As a result, highly reliable packages with various die sizes, including 5.2x5.2, 7.2x7.2 and 10.3x10.3 mm2 and with both 400 and 350 µm ball pitches have been developed. The RDL within the package of UFI WLCSP can be utilized to form inductor structure which exhibits quality-factor nearly 50% higher than that of an on-chip inductor. Besides, in WLCSP process, die sawing typically causes delamination and cracking of packages which results in process failure in the WLCSP. The UFI unique structure consists of sidewall protection which is capable of preventing chipping and therefore effectively improves the process controls and the reliability margins. In addition, to fulfill the requirement of high I/O products and to enhance the design flexibility, we embedded multiple RDL in UFI WLCSP with die size of 10.3x10.3 mm2 and ball pitch of 350 µm, which provides a fan-in package solution with I/O >800. The large die UFI WLCSP has passed the component-level reliability tests of TCB1000, uHAST96 and HTS1000, and board-level reliability tests of TCG500 and drop tests.

In this work, a systematic study was performed in order to evaluate the influences of chip scale package (CSP) materials on the reliability of the soldered joints. The type of adhesive interconnecting the top and bottom layers of silicon was varied in this study. The materials alternatives evaluated comprise a hard epoxy material with high filler content, a rubber-like adhesive and an adhesive in medium state. These were combined with the substrate materials, FR4 and Al/sub 2/O/sub 3/, on which the CSPs are mounted. A unified viscoplastic constitutive model was applied to represent the temperature and time dependent deformation behaviour of the solder material. The stress/strain responses of CSP solder joints under thermal cycling conditions were evaluated using the finite element method. From the results, solder joint lifetimes were estimated with a crack propagation model. The results show that under thermal cycling conditions, the CSP solder joint lifetimes are lower when the CSP is fabricated with a highly filled adhesive compared to those with a rubber-like adhesive. Also, the solder joint reliability of CSPs mounted on FR4 substrates is inferior to those on Al/sub 2/O/sub 3/ substrates. This is due to the fact that the internal adhesive layer in a CSP also serves as the source of thermal expansion mismatch. Furthermore, a more flexible CSP design can reduce stresses in the soldered joints. Some discussions for material selection of epoxy adhesive in CSP are also presented. Consequently, a structural adhesive with a low elastic modulus and low CTE is more desirable than a harder material.

RDL (Re-Distribution Layer) structure is an interim product to link up IC chip for wire bonding and flip chip assembly. We can perform area array solder bumps on a chip with peripheral IC pads by means of RDL rerouting technology, and the re-design and re-fabrication procedures of IC chip will not be required. The flip chip technology not only offers miniaturized packaging and higher I/O count but also has better electrical, thermal and reliability performances in comparison with traditional wire bonding. In this study, we investigate how to enhance the reliability property of solder bump with RDL structure by means of materials utilization, bump design and process optimization. In Chapter 1, how WLCSP works and its benefits will be described. Under traditional gold wire design , the I/O pad of IC with peripheral pad turn to area array by RDL rerouting technology. In Chapter 2, the issues faces under RDL process re mentioned, including di-electric de-lamination due to bad adhesion, howthe adhesion improved, and the comparions between different bump structure, with various de-electric selection. Chapter 3 illustrates experiment design, Chapter 4 discusses the testing results from those samples which pass Reliability test , and result in raise Reliability of RDL technology . The end product of this thesis is a WLCSP package composed of bare die onto FR4 substrate without underfill. The optimal design of RDL structure in the study has been qualified and passed wafer-level and board-level reliability tests, including temperature cycling test for 1000 cycles from -55C to 125C

Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm 2 body size, 18×15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a -40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.

The demand on reliable Wafer level chip scale packages (WLCSP) are getting higher due to the need of small form factor and cost. As demonstrated in earlier publications the degradation and deformation mechanism show microstructure evolution associated with the thermal cycling induced damage accumulation. The mechanism, leading to crack initiation and propagation during thermal cycling by sub-grain boundary development can be observed as a general damage accumulation mechanism in various solder joints. The correlation between crack propagation and localized recrystallization are compared in a series of cross section analyses on thermal cycled WLCSP components with normal and elevated temperature thermal cycling conditions. Damage accumulated solder joint locations are identified and an attempt of using edge-bond materials to strengthen the localized solder joints demonstrate that the Tg and CTE needs adjustment to have the thermal cycling performance enhancement. Edge-bond material applied components show either a shift of damage accumulation to a more localized region, thus potentially accelerated the degradation, or mitigate the distribution resulting in an enhancement of thermal cycling based on their Tg and CTE properties. The edge-bond applied WLCSPs were thermally cycled from 0oC to 100oC with 10min. dwell time, and to simulate the function temperature environment, components were also tested at elevated temperature cycles for comparison. Using an analysis on localized distribution of recrystallized areas inside the solder joint provide more information on the localized microstructure evolution during thermal cycling. The results show that the crack propagation distribution and recrystallization region correlation can explain the enhancement and potential degradation mechanisms and support the damage accumulation history in a more efficient way.

This paper describes a novel wafer level package using a silicone under the bump (SUB) design. The SUB architecture is designed to access the elastomeric qualities of silicones to reduce stresses on solder joints in a chip scale package. Poor reliability of the solder joints frequently arises from stresses generated by the mismatch in coefficient of thermal expansion between the die and the printed circuit board (PCB). Integration of a low modulus silicone pad between the die and solder ball allows for additional deformation mechanisms to dissipate stress between the die and the PCB during thermal cycling, increasing device reliability. Key to the realization of a SUB device was the integration of an elastomeric pad using the recently commercialized Dow Corning/sup /spl reg// WL-5150 photodefinable spin-on silicone. SUB devices containing 40 /spl mu/m thick silicone pads were successfully built using a series of standard processing steps including photolithography, plasma cleaning, and metallization. Two different SUB solder joint designs, suggested by FEA, were constructed and evaluated under thermal cycling. Failure mechanisms in the devices were determined to be dependent on the metallization scheme for the electronic connections. Incorporation of the silicone pads in a SUB device resulted in a 90% increase in reliability relative to control devices without the silicone pad. The failure mechanisms observed suggested an intermediate metallization approach to further enhance reliability.

We developed a highly reliable fan-out-type chip scale package (CSP) for a microcomputer or an ASIC (Application Specific IC) . We found that the solder joint reliability of the CSP under temperature cycling is equal to that of a quad flat package (QFP) and that its mechanical strength (determined from a board-bending test) is much higher than that of a QFP. The fatigue life of a Sn-Ag-Cu lead-free CSP solder joint determined from a cyclic board-bending test is almost equal to that of a Sn-37Pb CSP solder joint. Moreover, compared to a QFP, the occupied area of a CSP is decreased by 75% and its weight is decreased by 90%.

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is investigated in this study. The 62Sn36Pb2Ag solder joints are assumed to be: an elastic material; an elastic‐plastic material; and a creep material which obey the Garofalo‐Arrhenius steady‐state creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented herein will be compared with that from creep analysis of the WLCSP on PCB without microvia build‐up layer.

Recently the package market is demanding the smaller package size and the lower impedance electrical path with a short interconnection. The wafer level chip scale package is one of them, which has the solution of the market needs above. However, WLCSP technology is still not fully accepted on the large device size that is larger than 5mm × 5mm. It needs to overcome 2nd level reliability issue on both solder joint and drop reliability test. To improve 2nd level reliability, we need to apply the longer stand–off design such as Cu –post and double solder ball instead of single solder ball, and low modulus material on polymer layer under the solder pad for releasing thermal stress which result in the solder joints crack due to CTEs (Coefficient of Thermal Expansion) mismatch between organic PCB and WLCSP. In this paper, the double ball structure is introduced as one of them can provide the longer stand off. In addition of improving 2nd level reliability and drop test it may need to apply different solder ball component properties to increase Thermal cycling and drop test. The WLCSP structured a double solder ball showed a better 2nd level reliability result. This paper describes the molding process for double ball process and 2nd level reliability by solder property variation.

One of the main challenges in the electronics manufacturing and packaging development is how to integrate more functions inside the same or even smaller size. To meet the demand for higher integration, the interest toward passive and active component embedding has been increasing during the past few years. One of the main reasons for the growing interest toward embedded active components, in addition to demand for higher packaging density, is the need for better electrical performance of the component assemblies. However, it is little known how embedded IC and passives affect the reliability of IC packaging. Solder joints have been used in the electronic industry as both structural and electrical interconnections between electronic packages and printed circuit boards (PCB). When solder joints are under thermal cyclic loading, mismatch in coefficients of thermal expansion (CTE) between the printed circuit boards and the solder balls creates thermal strains and stresses on the joints, which may finally result in cracking. Consequently, the mechanical interconnection is lost, leading to electrical failures (such as hard/intermittent open, parametric failure), which in turn causes malfunction of the circuit or whole system. When a die is embedded into a substrate, Young's modulus of the die is larger than one of the core of the substrate and the CTEs of the die is smaller than those of the substrate. As a result, mismatch in coefficients of thermal expansions (CTE) between the substrate with the embedded device and the solder balls may increase. In the present study, the stress of chip scale packages (CSP) with an embedded die under thermal cycling conditions is evaluated using the finite element method. The viscoplastic model for solders including matrix dislocation mechanism and grain boundary sliding model developed by Yi et al. (2002) is employed.

Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layers on the solder joint reliability of WLCSP on printed circuit boards (PCB) through creep responses such as deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped WLCSPs with pad-redistribution are considered in this study.

The effect of a 2-layer microvia build-up printed circuit board (PCB) on the solder joint reliability of a wafer level chip scale package (WLCSP) assembly subject to thermal cycling is investigated in this study. The 62Sn-2Ag-36Pb solder joints are assumed to be: (1) an elastic material; (2) an elastic-plastic material; and (3) a creep material described by the Garofalo-Arrhenius creep constitutive equation. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three analyses. Besides, the present results are compared with those from the previous analyses on the WLCSP assembly with only one microvia build-up layer.

The solder on rubber (SOR) interconnection design and its reliability assessment based on shear strength test and finite element analysis

Chip scale package (CSP) as an advanced technology has been applied to LED lighting devices, besides electromigration (EM) in CSP under high current density has become a critical reliability issue for the future high density microelectronic packaging. In this paper, the thermal-electric-mechanical coupled analysis is performed by the flip-chip CSP LED multi-physical finite element model. Based on the atomic flux divergences (AFD) method, the position of void formation in the solder joints is predicted subsequently. Influences of the ambient temperature and applied current on the EM failure life of LEDs are investigated finally.