Multiple impact characterization of wafer level packaging (WLP)

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

A low-cost, highly reliable UFI (UBM-free integration) wafer level chip scale packaging (WLCSP) for high performance, large die (>100 mm2) with fine solder ball pitch (350 µm) and high I/O (>800) has been developed. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5x5 mm2 with ball pitch smaller than 350 µm. In this paper, we present the novel WLCSP designed with a stress-mitigation structure which can significantly enhance the reliability of the package and enables die size extension. By controlling the maximum strain location and optimizing the materials using the stress-mitigation structure, the chip warpage and the stress between Si and PCB can be effectively reduced to enhance both component and board-level reliabilities of the package. The UFI WLCSP passed all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution (t63), respectively. As a result, highly reliable packages with various die sizes, including 5.2x5.2, 7.2x7.2 and 10.3x10.3 mm2 and with both 400 and 350 µm ball pitches have been developed. The RDL within the package of UFI WLCSP can be utilized to form inductor structure which exhibits quality-factor nearly 50% higher than that of an on-chip inductor. Besides, in WLCSP process, die sawing typically causes delamination and cracking of packages which results in process failure in the WLCSP. The UFI unique structure consists of sidewall protection which is capable of preventing chipping and therefore effectively improves the process controls and the reliability margins. In addition, to fulfill the requirement of high I/O products and to enhance the design flexibility, we embedded multiple RDL in UFI WLCSP with die size of 10.3x10.3 mm2 and ball pitch of 350 µm, which provides a fan-in package solution with I/O >800. The large die UFI WLCSP has passed the component-level reliability tests of TCB1000, uHAST96 and HTS1000, and board-level reliability tests of TCG500 and drop tests.

A plastic chip-scale package (CSP) smaller than conventional packages has been developed and applied to ATM switching systems. The package uses a low-cost glass-epoxy substrate. As glass epoxy is widely used in the printed circuit boards (PCBs) of ATM switching systems, its use in the CSPs mounted on a PCB reduces the difference in thermal expansion between PCB and CSPs, thus lengthening CSP life. The power plane, ground plane, and thermal vias of the CSP are designed to offset the increased thermal resistance due to the CSP's smaller size. Simulation showed a thermal resistance for this CSP with copper layers and thermal vias of as much as 22% less than that of a CSP with no copper layers or thermal vias. A six-layer test board mounting four CSPs was used to simulate a sub-board for ATM switching systems. The thermal resistance of the two CSPs located downstream was about 10% higher than that of the two located upstream. Two CSPs were developed for two types of application-specific ICs: a bus interface controller (BIC) and a peripheral interface circuit (PIC). Both CSPs were 18 mm square with a 0.8 mm outer solder-ball pitch and 256 outer balls. These CSPs occupied areas about 87% and 68% smaller than those of a conventional pin grid array (PGA) and quad flat package (QFP) respectively. The junction temperature of both CSPs satisfied the thermal conditions. These high-performance CSPs are thus attractive for use in ATM switching systems.

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (<2.5mm), low pin counts (<25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is subject to the price-pressure that accompanies this transition. More recently, the semiconductor industry has seen advances in WLCSP technology which have enabled the qualification envelope to be expanded to products with pin counts > 120. These advances have facilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory, many of which require advanced silicon technology nodes as well. Consequently, WLCSP is expanding to markets and applications previously supported by QFN and flip chip CSP. This expansion puts additional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is further enhanced by the changing business models and supply chain strategies adopted by companies in the new economic environment. To meet these growing market demands, WLCSP providers are faced with the challenges of providing faster cycle times and higher capacity without significant increases in capital expenditure. The above factors have driven the need for new WLCSP technologies that utilize fewer process steps compared to common WLCSP product offerings, while maintaining the robustness necessary for meeting quality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to cater to the cost and performance requirements of the diverse application space. This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows. This paper will examine material options, i.e., polymers and solder alloys, for these new structures and will also examine the effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modes produced during reliability testing will be coupled with mechanical simulations to enhance understanding of the failure mechanisms and to further strategies for improving product reliability.

This paper documents a chip scale package (CSP) cost analysis using SEMATECH's Cost/Resource Model (CRM). The intent of the analysis was to compare costs between CSPs and conventional package technologies such as the thin small outline package (TSOP) and ball grid array (BGA) to determine whether CSP is a viable packaging technology. The analysis includes costs of both package and board assembly components in a high volume, mature production factory. Four representative CSP types (custom lead frame, flex circuit interposer, rigid substrate interposer, and wafer level assembly) and three traditional surface mount package configurations (plastic ball grid array [PBGA], ceramic ball grid array [CBGA], and thin small outline package [TSOP]) were selected to benchmark. By selecting CSPs across many applications and I/O ranges, the goal was to study a cross section of CSPs that were in or near production. Analysis results indicated that CSPs with a low I/O count are cost-competitive with conventional surface mount packages and can be used with the existing printed circuit board (PCB) infrastructure. However, CSPs with a high I/O count are not currently supported by conventional PCB technology and are not cost-competitive with conventional surface mount package technology.

Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layers on the solder joint reliability of WLCSP on printed circuit boards (PCB) through creep responses such as deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped WLCSPs with pad-redistribution are considered in this study.

The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is investigated in this study. The 62Sn36Pb2Ag solder joints are assumed to be: an elastic material; an elastic‐plastic material; and a creep material which obey the Garofalo‐Arrhenius steady‐state creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented herein will be compared with that from creep analysis of the WLCSP on PCB without microvia build‐up layer.

To enable richer consumer experiences, more IC chipsets with various functionalities and greater memory density have been deployed in the limited phone board area. A new generation of surface mount devices such as fine pitch BGA, package-on-package (POP), and wafer-level packaging, are being introduced to reduce board area for the given feature set. Board level reliability of new packages is one of the most important aspects to system performance under impact loadings. The dynamic reliability characterization of the components has been used as a basis for predicting a system (phone) level reliability. Package characterization methodologies must be designed to capture the interconnect failure modes of the actual IC packages commonly encountered in phone drop conditions for better prediction of phone-level reliability. Strain gage measurements and finite element analysis (FEA) of drop tests performed on portable electronic devices revealed mixed printed circuit board (PCB) flexural modes during impact. Dynamic planar and spherical bend tests were developed to study the effect of PCB bend mode on solder interconnect reliability. In the present study, a planar flexural mode was generated through utilization of a 4-point bend test fixture, and a spherical bend test was developed to achieve an equi-biaxial strain state at the vicinity of a corner solder joint as opposed to predominantly uni-directional strain state in four-point bend test. A failure prediction model based on connector finite element modeling was developed to understand the significantly different solder joint reliability under the two loading conditions. The ability of the new modeling technique to accurately predict failure of solder joints under different loading conditions was appreciated showing excellent agreement to failure analysis of actual test samples. The new methodology can enable efficient and accurate means of assessing package reliability under various conditions that simulate portable electronic devices being dropped in the field.

In the last decade, the Ultra-Thin HDI (High Density Interconnect) technology has dominated the mobile/wearable products designs, yet the standard test vehicles used for qualifying materials, components and connectors provided by IPC (Institute of Printed Circuits), ANSI (American National Standard Institute) and JEDEC (Joint Electron Device Engineering Council aka Solid State Technology Association), are obsolete and OEM’s (Original Equipment Manufacturer) have stopped using them. These test vehicles do not reflect the form factors, density and interconnect methods used by the industry. In addition, they do not capture failure modes of the fine pitch BGA (Ball Grid Array) technology and as a result don’t provide upstream Users adequate data for development. Microvias and dielectrics are the key, along with finer lines and spaces, in obtaining the density of Ultra-Thin HDI boards. Continuous reduction in PCB dimensions and feature sizes challenges both fabrication process and test vehicles. HDP User Group’s paper gives a brief introduction to the modern Ultra-Thin PCB (Printed Circuit Board) fabrication process. It discusses typical board level reliability tests and presents a generic reliability test vehicle design which is based on current Ultra-Thin HDI technology. With the proposed test vehicles’ design of modularity and scalability it is easy to modify to meet the next generation of Ultra-Thin HDI PCB requirements. The study indicates that the proposed TV design covers HDI test requirements and most of the current tests are critical when evaluating modern Ultra-Thin HDI circuit board reliability. The HDP User Group project also conducted a study on the application and reliability of a very fine pitch WLCSP (Wafer Level Chip Scale Package) on this Ultra-Thin HDI test vehicle. A 0.3mm pitch WLCSP daisy chain, commercially available solder paste, flux and underfill were used for this study. The details of the assembly process including solder paste printing, dip flux, component placement, reflow and underfill dispensing are discussed. The impact of the test vehicle OSP (Organic Surface Protection) surface finish on the assembly process and result is addressed as well. JEDEC standard air-to-air thermal cycling and drop tests are performed for reliability evaluation purposes. The reliability data of solder paste printing vs. dip flux, underfill vs. non-underfill are compared and evaluated. All results show that the WLCSP application process and materials on the ultra-thin test vehicle are robust and reliable.

The effect of a 2-layer microvia build-up printed circuit board (PCB) on the solder joint reliability of a wafer level chip scale package (WLCSP) assembly subject to thermal cycling is investigated in this study. The 62Sn-2Ag-36Pb solder joints are assumed to be: (1) an elastic material; (2) an elastic-plastic material; and (3) a creep material described by the Garofalo-Arrhenius creep constitutive equation. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three analyses. Besides, the present results are compared with those from the previous analyses on the WLCSP assembly with only one microvia build-up layer.

Ball Grid Array (BGA) packages with 1.27 mm pitch arrays are now being extended to fine pitch BGAs, or Chip Scale Packages (CSP) with ball diameters of 0.3 mm and array pitches as small as 0.5 mm. The current work analyzes the impact of integrating such packages into a high volume SMT assembly line and examines the impact of process and board variables on the reliability of the total assembly. The CSP chosen for the current study was a 0.75 mm pitch CSP scheduled to replace the 0.5 mm lead pitch Thin Small Outline Package (TSOP) currently used in high volume, small form factor, flash memory products. The CSP dimensions of approximately 5.6 mm by 7.4 mm represents an 80% reduction in package area compared to the traditional TSOP, with a footprint of 12 mm by 20 mm. The study examines the effect of solder paste printing parameters, flux-only assembly, and printed circuit board surface finishes such as immersion gold and solder-leveling. Solder paste volume measurements were made on over 2800 individual CSP pads during the builds using an in-line, automated laser scanning profilometer. Reliability test vehicles were assembled using CSPs, TSOPs and other surface mount components, prior to performing accelerated thermal cycling tests from 0/spl deg/C to 100/spl deg/C, and 40/spl deg/C to 85/spl deg/C. CSP placements were performed using optimized high speed chip placers to place CSPs at rates of up to 5 parts per second. Interim reliability test results after four months of testing are presented with a discussion of TSOP versus MicroBGA package construction.

Along with the trends of the product minimization, wafer level chip scale package (WLCSP) has become a new solution to advanced packaging. Formation of micro-vias with desired patterns is a critical process step. Currently micro-vias are achieved through photolithographic technology, which is lengthy and time-consuming. In order to improve the productivity and reduce the cost of the via formation process, it is critical to develop a simpler and more cost-effective drilling technology. The successful application of laser drilling in printed circuit boards promted us to apply the technology in drilling microvias of WLCSPs. The critical new challenges of the laser drilling of WLCSPs are the requirements of forming straight-walled vias on a thin copper layer (less than 1 µm). The laser-drilled vias need to be free of residues for subsequent electroplating of copper bumps. In this paper, we report our experimental results using a Q-switched CO2 laser.Along with the trends of the product minimization, wafer level chip scale package (WLCSP) has become a new solution to advanced packaging. Formation of micro-vias with desired patterns is a critical process step. Currently micro-vias are achieved through photolithographic technology, which is lengthy and time-consuming. In order to improve the productivity and reduce the cost of the via formation process, it is critical to develop a simpler and more cost-effective drilling technology. The successful application of laser drilling in printed circuit boards promted us to apply the technology in drilling microvias of WLCSPs. The critical new challenges of the laser drilling of WLCSPs are the requirements of forming straight-walled vias on a thin copper layer (less than 1 µm). The laser-drilled vias need to be free of residues for subsequent electroplating of copper bumps. In this paper, we report our experimental results using a Q-switched CO2 laser.

The main objective of this study is to develop a stress-buffer-improved package that is subjected to a board level drop test under a specific-G impact level. In this regard, both the drop test experiment and the ANSYS/LS-DYNA simulations are carried out. Several studies have shown that the solder joints having the brittle intermetallic compound (IMC) layers within the wafer level chip scale packaging (WLCSP) are the weakest part. For the most part, this is due to the large relative motion occurring between the board and the chip. In addition, the stress buffer layer exhibiting a relatively large elongation which reduces the impact on the solder balls. Meanwhile, the novel stress-buffer-improve package's failure mode is different from the convention WLCSP structure which shifts to the trace damage of the chip side. The leading concern between the solder ball and trace damage is the critical region where failure occurred owing to the stress concentration effect. During the drop test experiment, the proposed stress-buffer-improved package is able to survive over 100 drops (most packages survived at above 200 drops). Hence, this drop performance very much surpasses the Joint Electron Device Engineering Council (JEDEC) criterion (drop number is 30 times). Nevertheless, the metal traces which are embedded in the stress buffer layer suffered relatively larger deformation. Generally, the stress concentration occurs at a single position, much like the trace/pad connecting junction in the analysis of detailed stress-buffer-improved package. Finally, the predict result in finite element (FE) analysis is similar to the broken metal trace's failure analysis in the drop test experiment.

Microelectronics devices continue to evolve towards increased functionality, thinner die, increased reliability, and reduced cost, requiring a change in material and process requirements for the next generation of packages (i.e. stacked chip packages and wafer level packages (WLP)). Stress reduction is a key factor for many devices, particularly those that have thinner die and those that are subjected to stresses generated by thermal cycling. Wafer level packaging is an area where low stress and high volume manufacturing are critical for achieving good reliability and low manufacturing cost. Dow Coming and IMEC have been investigating a Silicone Under the Bump (SUB) wafer. level package as a potential route towards increased reliability. Including a SUB design into the device architecture provides a route to dissipate the stresses generated by the thermal expansion mismatch between the silicon die and the printed circuit board. Key to the device build is the application of a silicone pad using a photosensitive silicone or a screen printable silicone. In the design, metal traces from the bonding pads are redistributed to the tops of the silicone pads. Solder balls are placed on the metallized pads to complete the interconnection. The elastomeric nature of the pad dissipates the stresses created by the mismatch in CTE between the chip and the PCB and extends device reliability. To build the SUB enabled WLP device it was critical to understand the impact of the new materials on the device process steps. The uniqueness of the material set requires the creation and optimization of plasma cleaning processes specific to silicones, direct-on-silicone metallization and metal etching in the presence of silicones. The application of a solder mask and solder ball placement is required to complete a successful device build. In this paper we will discuss in detail the process steps utilized in building a silicone containing WLP. This will include a discussion on the process challenges including silicone pad integration, metallization, solder mask application and solder ball placement. The methodologies described in this paper can be generally applied for integration of photopatternable silicones into a range of devices and packages.

This paper describes a novel wafer level package using a silicone under the bump (SUB) design. The SUB architecture is designed to access the elastomeric qualities of silicones to reduce stresses on solder joints in a chip scale package. Poor reliability of the solder joints frequently arises from stresses generated by the mismatch in coefficient of thermal expansion between the die and the printed circuit board (PCB). Integration of a low modulus silicone pad between the die and solder ball allows for additional deformation mechanisms to dissipate stress between the die and the PCB during thermal cycling, increasing device reliability. Key to the realization of a SUB device was the integration of an elastomeric pad using the recently commercialized Dow Corning/sup /spl reg// WL-5150 photodefinable spin-on silicone. SUB devices containing 40 /spl mu/m thick silicone pads were successfully built using a series of standard processing steps including photolithography, plasma cleaning, and metallization. Two different SUB solder joint designs, suggested by FEA, were constructed and evaluated under thermal cycling. Failure mechanisms in the devices were determined to be dependent on the metallization scheme for the electronic connections. Incorporation of the silicone pads in a SUB device resulted in a 90% increase in reliability relative to control devices without the silicone pad. The failure mechanisms observed suggested an intermediate metallization approach to further enhance reliability.