Cost analysis of chip scale packaging

Ball Grid Array (BGA) packages with 1.27 mm pitch arrays are now being extended to fine pitch BGAs, or Chip Scale Packages (CSP) with ball diameters of 0.3 mm and array pitches as small as 0.5 mm. The current work analyzes the impact of integrating such packages into a high volume SMT assembly line and examines the impact of process and board variables on the reliability of the total assembly. The CSP chosen for the current study was a 0.75 mm pitch CSP scheduled to replace the 0.5 mm lead pitch Thin Small Outline Package (TSOP) currently used in high volume, small form factor, flash memory products. The CSP dimensions of approximately 5.6 mm by 7.4 mm represents an 80% reduction in package area compared to the traditional TSOP, with a footprint of 12 mm by 20 mm. The study examines the effect of solder paste printing parameters, flux-only assembly, and printed circuit board surface finishes such as immersion gold and solder-leveling. Solder paste volume measurements were made on over 2800 individual CSP pads during the builds using an in-line, automated laser scanning profilometer. Reliability test vehicles were assembled using CSPs, TSOPs and other surface mount components, prior to performing accelerated thermal cycling tests from 0/spl deg/C to 100/spl deg/C, and 40/spl deg/C to 85/spl deg/C. CSP placements were performed using optimized high speed chip placers to place CSPs at rates of up to 5 parts per second. Interim reliability test results after four months of testing are presented with a discussion of TSOP versus MicroBGA package construction.

Fine-pitch ball grid array (BGA) and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in automotive underhood environment is not well understood. In this work, the reliability of fine-pitch plastic ball grid array (PBGA) packages has been evaluated in the automotive underhood environment. Experimental studies indicate that the coefficient of thermal expansion (CTE) as measured by thermomechanical analyzer (TMA) typically starts to change at 10-15/spl deg/C lower temperature than the T/sub g/ specified by differential scanning calorimetry (DSC) potentially extending the change in CTE well into the accelerated test envelope in the neighborhood of 125/spl deg/C. High T/sub g/ substrates with glass-transition temperatures much higher than the 125/spl deg/C high temperature limit, are therefore not subject to the effect of high coefficient of thermal expansion close to the high temperature of the accelerated test. Darveaux's damage relationships were derived on ceramic ball grid array (CBGA) assemblies, with predominantly solder mask defined (SMD) pads and 62Sn36Pb2Ag solder. In addition to significant differences in the crack propagation paths for the two pad constructions, SMD pads fail significantly faster than the non solder mask defined (NSMD) pads in thermal fatigue. The thermal mismatch on CBGAs is much larger than PBGA assemblies. Crack propagation in CBGAs is often observed predominantly on the package side as opposed to both package and board side for PBGAs. In the present study, crack propagation data has been acquired on assemblies with 15, 17, and 23mm size plastic BGAs with NSMD pads and 63Sn37Pb on high-T/sub g/ printed circuit boards. The data has been benchmarked against Darveaux's data on CBGA assemblies. Experimental matrix also encompasses the effect of bis-maleimide triazine (BT) substrate thickness on reliability. Damage constants have been developed and compared against existing Darveaux Constants. Prediction error has been quantified for both sets of constants.

A plastic chip-scale package (CSP) smaller than conventional packages has been developed and applied to ATM switching systems. The package uses a low-cost glass-epoxy substrate. As glass epoxy is widely used in the printed circuit boards (PCBs) of ATM switching systems, its use in the CSPs mounted on a PCB reduces the difference in thermal expansion between PCB and CSPs, thus lengthening CSP life. The power plane, ground plane, and thermal vias of the CSP are designed to offset the increased thermal resistance due to the CSP's smaller size. Simulation showed a thermal resistance for this CSP with copper layers and thermal vias of as much as 22% less than that of a CSP with no copper layers or thermal vias. A six-layer test board mounting four CSPs was used to simulate a sub-board for ATM switching systems. The thermal resistance of the two CSPs located downstream was about 10% higher than that of the two located upstream. Two CSPs were developed for two types of application-specific ICs: a bus interface controller (BIC) and a peripheral interface circuit (PIC). Both CSPs were 18 mm square with a 0.8 mm outer solder-ball pitch and 256 outer balls. These CSPs occupied areas about 87% and 68% smaller than those of a conventional pin grid array (PGA) and quad flat package (QFP) respectively. The junction temperature of both CSPs satisfied the thermal conditions. These high-performance CSPs are thus attractive for use in ATM switching systems.

Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic Ball Grid Array (BGA) packages. IBM has developed both Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packages which cover a wide range of package I/O capabilities required for high-performance devices, typically between 300 to more than 1600 I/O. Recently, there has been a lot of interest in Pb-free solders to replace typical Pb-based solders such as eutectic Sn-Pb used for balls in plastic BGAs (PBGA) for their assembly. The common feature of all proposed Pb-free solder alloys to date is that they are all Sn-based solders with the wt.% of Sn in the alloy typically greater than 90%. Antimony-based lead-free solders have been considered, but recently there has been a concern over the use of antimony (Sb) as well. The leading antimony-free (Sb-free) solder that has emerged from various Pb-free solder evaluations by industry and academic consortia at present is: 95.5Sn/3.8Ag/0.7Cu (SAC). The primary issues with changing from high-Pb based solders that are used in BGA assembly to electronic cards are: (1) wettability of the Pb-free solders to both Ni/Au I/O pads typically used in ceramic BGAs and card lands (Cu or Cu tinned with solder paste) with water soluble or no-clean fluxes; (2) the rate of intermetallic growth and its structure, with much higher Sn containing Pb-free solders; and (3) thermal fatigue reliability of the CBGA joints to organic cards. In this paper, initial assessment of a few leading Pb-free solders regarding wettability, microstructure and thermal fatigue life for CBGA applications is presented.

The use of PBGA (plastic ball grid array) is increasing with the spread of semiconductor package mounted on high-density printed circuit board. The solder joint reliability of PBGA has unresolved problems when compared with TSOP (thin small outline package) and QFP (quad flat package). The solder joint reliability under dropping impact of PBGA used in PDA (personal device apparatus) is under discussion nowadays. Though the relationship between solder joint reliability and surface finishes has been reported by many companies, there is no clear and noticeable trend. Therefore, we developed a high-speed shear test that simulates the drop-impact conditions. We also developed an electroless Ni-P/Pd/Au plating of good reliability for solder joint. Solder joint reliability is evaluated by the ball shear test. The shear strength and the fracture mode are influenced by shear speed. When lowspeed shear test was conducted, the effect of surface finish on the solder joint reliability was not apparent. But, when the highspeed shear test was used, the solder joint reliability to different surface finishes became clear. The high-speed shear test revealed that immersion Au lowered solder joint reliability during the electroless Ni-P/Au plating process. The cross-section of the electroless Ni-P/ immersion Au layers was observed by FIB/SIM (focused ion beam/scanning ion-beam microscopy). From FIB/SIM observation, we found that the corrosion on the surface of the electroless Ni-P with immersion Au had reduced the solder joint reliability. Some different methods to prevent the corrosion on the surface of the electroless Ni-P were studied and we found out that electroless Pd plating over electroless Ni-P was very effective. To conclude, the solder joint reliability of PBGA with electroless Ni-P/Pd/Au is equal to that of OSP (Organic Solder Preservation) and electrolytic Ni/Au.

Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layers on the solder joint reliability of WLCSP on printed circuit boards (PCB) through creep responses such as deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped WLCSPs with pad-redistribution are considered in this study.

The continued need for higher density designs with advanced electronic packaging technologies such as Ball Grid Array (BGA) and Chip Scale Packaging (CSP) and other commercial component technologies are important to Raytheon. Due to the costs associated with the development of certain high performance products, there is a critical need within Raytheon to develop rework capability of assemblies using these technologies. Unlike the commercial arena which produces high volume - low cost products such as cell-phones, personal digital assistants (PDA), computers and digital cameras, to name a few, the products developed by Raytheon Electronic Systems are considered low volume - high cost. The economics of the commercial arena indicate that reworking an electronic assembly is more the exception than the rule, whereas rework is a critical requirement for Raytheon. This paper will cover BGA/CSP rework, the process of repairing/modifying Printed Wiring Boards (PWB) when using these packages and the benefits associated with having this capability. In addition, we will highlight some of the lessons learned through our in–house process development. These capabilities stem from the leveraging of packaging technology development of the JPL/NASA led consortium, which Raytheon has been a member for the past seven years.

The measure of package performance depends on the specific application. A high speed, high I/O application poses many restrictions on the required performance in terms of thermal management, reliability as well as electrical integrity. Electrical performance issues have become a very significant performance figure with the increasing circuit density and faster rise time contrary to the traditional view of a package. The drive towards higher chip I/O, reducing device dimensions and demand for lower inductance is forcing many to abandon the traditional chip bonding techniques such as wire-bonding and pursue flip-chip techniques (i.e,, C4). The chip carrying substrate facilitates the fanning-out of the I/Os, powering up the chip, and providing I/O interface to the next level. A host of substrate technologies are available, In this paper we look at the trade offs between PBGA (Plastic Ball Grid Array) and CBGA (Ceramic Ball Grid Array) solutions from an electrical performance, package design and application point of view.

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Multiple impact characterization of wafer level packaging (WLP)

In the last decade, the Ultra-Thin HDI (High Density Interconnect) technology has dominated the mobile/wearable products designs, yet the standard test vehicles used for qualifying materials, components and connectors provided by IPC (Institute of Printed Circuits), ANSI (American National Standard Institute) and JEDEC (Joint Electron Device Engineering Council aka Solid State Technology Association), are obsolete and OEM’s (Original Equipment Manufacturer) have stopped using them. These test vehicles do not reflect the form factors, density and interconnect methods used by the industry. In addition, they do not capture failure modes of the fine pitch BGA (Ball Grid Array) technology and as a result don’t provide upstream Users adequate data for development. Microvias and dielectrics are the key, along with finer lines and spaces, in obtaining the density of Ultra-Thin HDI boards. Continuous reduction in PCB dimensions and feature sizes challenges both fabrication process and test vehicles. HDP User Group’s paper gives a brief introduction to the modern Ultra-Thin PCB (Printed Circuit Board) fabrication process. It discusses typical board level reliability tests and presents a generic reliability test vehicle design which is based on current Ultra-Thin HDI technology. With the proposed test vehicles’ design of modularity and scalability it is easy to modify to meet the next generation of Ultra-Thin HDI PCB requirements. The study indicates that the proposed TV design covers HDI test requirements and most of the current tests are critical when evaluating modern Ultra-Thin HDI circuit board reliability. The HDP User Group project also conducted a study on the application and reliability of a very fine pitch WLCSP (Wafer Level Chip Scale Package) on this Ultra-Thin HDI test vehicle. A 0.3mm pitch WLCSP daisy chain, commercially available solder paste, flux and underfill were used for this study. The details of the assembly process including solder paste printing, dip flux, component placement, reflow and underfill dispensing are discussed. The impact of the test vehicle OSP (Organic Surface Protection) surface finish on the assembly process and result is addressed as well. JEDEC standard air-to-air thermal cycling and drop tests are performed for reliability evaluation purposes. The reliability data of solder paste printing vs. dip flux, underfill vs. non-underfill are compared and evaluated. All results show that the WLCSP application process and materials on the ultra-thin test vehicle are robust and reliable.

This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies. Acceleration induced failure mechanisms varied from conventional surface mount (SM) failures for CSPs. Examples of unrealistic life projections for other CSPs are also presented. The cumulative cycles-to-failure for ceramic BGA assemblies performed under different conditions, including plots of their two Weibull parameters, are presented. The results are for cycles in the range of −30°C to 100°C, −55°C to 100°C, and −55°C to 125°C. Failure mechanisms, as well as cycles to failure for thermal shock and thermal cycling conditions in the range of −55°C to 125°C, were compared. Projection to other temperature cycling ranges using a modified Coffin-Manson relationship is also presented. [S1043-7398(00)00104-3]

While the electronics industry continues to strive toward miniaturization, it is important to understand that without standardization. The infrastructure will not exist in a cost effective timely manner for the new designed configurations of Ball Grid Arrays (BGAs) / Chip Size Packages (CSPs). The infrastructure is the immediate Package Interface. This would include the following: Shipping Tubes, Shipping Trays, Tape and Reels, Test Sockets, Burn-In Sockets, and Assembly Boards. The standardization effort helps the infrastructure suppliers to plan to meet the needs of the growing BGA / CSP industry. The lack of standardization will impact the final cost to the customer as well as their ability to get to market within the small window the supplier has for the product introduction. The major issue is the loss of time, which is the critical cost in the Semiconductor Market's short life cycles. A new package configuration at a high cost or late to the market place will not be a winner. The standardization must also occur not only regionally like JEDEC (USA) and EIAJ (JAPAN) but it must be taken to the next level. The next level in packaging is IEC (International) TC-47D. It is of the primary importance to reduce the possible variations while not limiting the customer's ability to select the most reliable cost-effective package for his or her market application. The introduction of Ball Grid Array packages has created a packaging concept for the board assembler that has allow them to go back to older equipment for pick and place as well as not having to worry about peripheral leaded package coplanarity and bend or skewed leads. The BGA has also reduced the concern of the assembler placing fine pitch (0.50, 0.40, 0.30 and lower mm) peripheral leaded packages. The disadvantage of the BGA / CSP package is that it is an array style package and can have many variations of ball pitches, ball sizes and ball counts for each body size. A CSP (Chip Size Package) is basically a thinner, smaller, and a finer pitch version of a BGA. This flexibility makes the need for Standardization more critical than is was for peripheral leaded packages.

The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is investigated in this study. The 62Sn36Pb2Ag solder joints are assumed to be: an elastic material; an elastic‐plastic material; and a creep material which obey the Garofalo‐Arrhenius steady‐state creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented herein will be compared with that from creep analysis of the WLCSP on PCB without microvia build‐up layer.

The growing integration of larger Ball Grid Arrays (BGAs), ceramic packages, and Wafer-Level Chip Scale Packages (WLCSPs) into automotive and other harsh-environment electronic systems necessitates enhanced reliability in printed circuit board (PCB) assemblies. These demanding environments—characterized by elevated thermal loads, mechanical stresses such as vibration and shock, and stringent operational requirements—pose significant challenges to the structural integrity and performance of electronic components. As advanced packaging technologies continue to evolve and design tolerances become more stringent, the selection and qualification of reinforcement materials, including underfills and Edgebond adhesives, have become increasingly critical. To meet the elevated reliability standards required in these conditions, advanced reinforcement strategies are being adopted, including the use of high-reliability solder alloys, flowable underfills, and no-flow Edgebond materials. Flowable underfills provide mechanical stability by fully encapsulating the interstitial spaces beneath components, while Edgebond materials are applied along the periphery of packages to enhance edge support and streamline assembly processes. The optimal reinforcement approach is influenced by multiple factors, including device architecture, warpage behavior, I/O pitch, and production throughput constraints. This study presents a comparative analysis of high-reliability solder alloys in combination with underfill and Edgebond materials to enhance the mechanical and thermomechanical durability of BGAs and WLCSPs for use in automotive and other high-stress environments. The evaluation encompasses a range of package sizes, I/O pitches, and warpage profiles, subjected to two distinct thermal cycling regimes. Mechanical reliability is assessed through vibration and mechanical shock testing, while thermomechanical performance is evaluated via thermal cycling. The results highlight the efficacy of specific material combinations and reinforcement strategies in improving the structural robustness of advanced electronic packages. These findings contribute to the development of next-generation packaging solutions capable of withstanding the rigorous demands of high-reliability applications in the automotive and industrial sectors.