Phison (Taiwan)

This paper presents the design, development, and deployment of a full-stack machine learning system for predicting loan repayment default, aimed at enhancing financial risk assessment. Utilizing the Home Credit Default Risk dataset from Kaggle, this study conducts a comparative analysis of three machine learning models: Logistic Regression, Random Forest, and XGBoost. The system architecture integrates a React frontend for user data collection and a Python Flask backend API that serves a serialized (.pkl) XGBoost model for real-time predictions. A key contribution of this work is the integration of SHapley Additive explanations (SHAP) to address the "black box" nature of complex models, providing transparent, feature-level interpretability for each prediction. The experimental results demonstrate that the XGBoost model achieves superior predictive performance, with a ROC-AUC score of 0.778. The application of SHAP successfully elucidates the key drivers behind individual predictions, making the model's decisions transparent and actionable for financial stakeholders. This project provides a practical blueprint for building and deploying interpretable, high-performance machine learning solutions that bridge the gap between theoretical modeling and real-world financial decision-making, thereby promoting more responsible and data-driven lending practices.

With the rapid development of positioning, localization, navigation, and self-driving car systems, the implementation of intelligent and robust localization systems for real-time location-based services (LBSs) has become increasingly attractive. This article presents high-performance positioning and tracking approaches characterized by a pipelined structure, high computational efficiency, flexibility, and real-time processing, implemented using field programmable gate arrays (FPGAs). In triangulation-based positioning approaches, estimated distance information is derived from communication signals and the path loss model, while vertical localization is achieved through the characteristics of barometric pressure (BP). After integrating positioning approaches with tracking methods and BP sensors, the results illustrate that the proposed localization algorithms closely estimate the trajectory of mobile devices. For FPGA-implemented algorithms, the proposed approaches effectively handle floating-point operations, reduce computing resource usage, and provide real-time processing capabilities, surpassing software-based designs and implementations. In terms of performance, the results demonstrate that the localization accuracy of the proposed hardware-based implementation is nearly identical to that of the software-based approach. Regarding vertical location accuracy, based on the proposed calibration approach, the BP value increases by 11.6 Pa for every one-meter decrease in altitude. To maintain floor-level accuracy over time despite atmospheric fluctuations, a real-time dynamic calibration mechanism using a fixed reference sensor is employed. In summary, the proposed localization algorithms, implemented with FPGAs and BP sensors, offer advantages such as lower circuit costs, higher processing efficiency, and reliable vertical location accuracy for real-time public safety LBS.

A method to reverse engineering of a fly brain using the {\it FlyCircuit} database is presented. This method was designed based on the assumption that similar neurons could serve identical functions. We thus cluster the neurons based on the similarity between neurons. The procedures are to partition the neurons in the database into groups, and then assemble the groups into potential modules. Some of the modules correspond to known neuropils, including Medulla were obtained. The same clustering algorithm was applied to analyze Medulla's structure. Another possible application of the clustering result is to study the brain-wide neuron connectome by looking at the connectivity between groups of neurons.

Compared to single-level-cell (SLC) mode operation, triple-level-cell (TLC) mode operation reduce NAND Flash lifetime due to its stronger program <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$/$ </tex-math></inline-formula> erase ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}/\text{E}$ </tex-math></inline-formula> ) cycled-induced oxide degradation and narrower read margin between neighboring states. However, by measuring the evolution characteristics of raw bit error rate (RBER) and threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {t}}$ </tex-math></inline-formula> ) shift during retention bake, TLC-erase <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$/$ </tex-math></inline-formula> SLC-program mix-mode <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}/\text{E}$ </tex-math></inline-formula> sequences in 3-D NAND Flash memory exhibits significant retention deterioration compared with pure TLC-mode <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}/\text{E}$ </tex-math></inline-formula> schemes. Based on our measurement results, mix-mode operation may create more residual holes in the inter-gate spacing (IGS) region, giving rise to enhanced lateral migration of trapped charge in silicon nitride (SiN) storage layer and the larger <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {t}}$ </tex-math></inline-formula> retention loss accordingly.

Diagnosis of intermittent scan chain failures still remains a hard problem. In this article, we demonstrate that the use of artificial neural networks (ANNs) can lead to significantly higher accuracy. The key of this method is a multistage process incorporating ANNs with gradually refined focuses. During this process, the final fault suspect is elected through multiple rounds of ANN inference, instead of just one round. At each stage, identification of a proper Affine Group, used as the “candidate set of scan cells for the next round of ANN inference,” will influence the final diagnostic accuracy. Thus, we propose a validation-based learning procedure for Affine Group derivation to further boost the final diagnostic accuracy. The experimental results on benchmark circuits have shown that this method is, on the average, 17.46% more accurate than a state-of-the-art commercial tool for intermittent stuck-at-0 faults.

A multi-mode Low-Density Parity-Check (LDPC) error correction engine with a Digital Signal Processing (DSP) module is presented for low power and ultra high reliability NAND Flash memory controllers. The DSP module improves the reliability of the storage systems via calculating the adaptive reliability information and translating the information into Log-Likelihood Ratio (LLR) for soft bit decoding. According to the experiment results on sub-20nm Triple Level per Cell (TLC) NAND Flash memory, the retention ability of LDPC with DSP is a 20 times improvement over BCH code and 2 to 5 times improvement over conventional LDPC. Moreover, the proposed decoder reaches a throughput over 400MB/s as well as a power consumption of 21.8mW under 40nm CMOS technology at 45 bit errors.

A new effective digital image stabilisation algorithm is presented. The proposed method adaptively compensates hand jitter in a two-dimensional framework. Performance evaluation based on the motion diagram and coding efficiency substantiates the superiority of the proposed algorithm.

In any motor control system consisting of more than one SCR phase-controlled variable voltage power supply, interaction can occur. Interaction within a system can result from several forms of interference: 1) high rates of current rise in the load di/dt which generate voltage wave fronts in excess of the SCRs withstand capability dv/dt; 2) transients generated in the system, coupling into the control, trigger, or gate circuits causing an SCR to conduct; 3) supply line distortion due to high reactive lines, causing degradation in system performance.