Renesas Electronics (Japan)

The author has previously shown that ultra-low energy levels exist among the energy levels of a hydrogen atom, in addition to the energy levels predicted by quantum mechanics. The author has also pointed out that the reduction in rest mass energy of the electron m e c 2 corresponds to potential energy of an electron inside a hydrogen atom. Based on this idea, when an electron that has been taken into the region of a hydrogen atom comes to the point of the classic electron radius r e , its potential energy becomes − m e c 2 , and the electron’s rest mass energy is depleted. Therefore, r e ≤r∞ is the region where the well-known formula for potential energy of an electron is applicable. Rest mass energy is not sufficient for an electron to approach closer than that to the atomic nucleus. Under these conditions, an electron cannot attain ultra-low energy levels. Thus, taking a hint from renormalization theory, the author has predicted that the energy of a stationary electron is actually not m e c 2 , and instead that the electron has a photon energy of 2 m e c 2 and a negative energy specific to the electron of − m e c 2 . When this model is used, it becomes possible for the electron to approach the point r= r e /4 regarded as the radius of the proton. This paper derives a new formula for potential energy of an electron in regions outside the scope of application of the existing formula for potential energy.

This paper presents an area-efficient assist architecture using a static noise margin (SNM) detector for high-density (HD) SRAMs that are particularly vulnerable to process variation. The SNM detector is arranged in the peripheral and composed of a logic SRAM cell with simple small logic circuits that is designed to be a replica of the least stable cell in order to reproduce the worst SNM characteristics. By using this detector, unneeded assist can be eliminated depending on PVT conditions, as a result, dramatical improvement of access time (25%) and reduction of active power (24.4% @ write and 32.8% @read) are achieved with the smallest area overhead (0.015%).

Because general-purpose microcontrollers (MCUs) handle input signals from wide variety of sensors, ADCs must support sampling frequencies of a few MHz, 16-bit resolution, and single-ended and common-free differential inputs. The ADC shown in Fig. 1(a) multiplexes input channels (CHs) to support low-cost multi-input systems, and uses oversampling techniques and digital filters to suppress noise from the CPU, RAM, ROM, and I/O. In addition, motor control applications require that the sampling skew of each CH must be suppressed. Therefore, as shown in Fig. 1(d), the input CH is switched by a multiplexer for each A/D conversion, and the output of the ADC is distributed to a digital filter dedicated to each CH by a demultiplexer. However, in such a system, the SNDR is degraded by interference with the residual signal from the previous channel due to the capacitor dielectric relaxation effect [1] [2]. The capacitor dielectric relaxation effect is a frequency-dependent change in capacitance that can be represented by a combination of several RC models. The problem is that the dielectric relaxation effect exists down to the low frequency bands in Fig. 1(b), so the speed of the ADC must be reduced, and this effect is especially significant in high accuracy ADCs.

Choosing a DfT architecture for heterogeneous multi-core SoCs is constrained by various business, design and industrial-test requirements. SSN is a bus-based packetized data distribution scan architecture designed to address these requirements. A comparison between SSN and previous hierarchical DfT approaches is shown. A specific project SoC requirements is reviewed with packetized scan delivery architecture trade-offs. Results show 2X scan data transfer rate while adhering to pinning, area and physical design constraints.

A low-supply-voltage low-phase-noise voltage-controlled oscillator (VCO) with harmonic tuning is presented. A novel LC tank is used to obtain better phase noise performance with no additional DC power consumption by providing high impedance at second harmonic. With a supply voltage of 300 mV, it is expected that the proposed LC-VCO IC achieves a phase noise of -107.2 dBc/Hz at 1 MHz offset from 12.02 GHz, with a minimum DC power consumption of 0.507 mW.

To solve social problems such as labor shortages, there are growing expectations for the advancement of human-cooperative robots. In such robots, advanced environmental recognition (mainly AI based), planning and control (normally non-AI algorithms) have to be processed simultaneously in real time. However, with current AI chips, meeting these objectives is challenging for several reasons: 1) A high-performance AI accelerator with 100TOPS peak class is required, in particular when a multi-camera system is employed for wide-range environment recognition. However, such an accelerator cannot be incorporated in a robot device because its power exceeds 10W [1] and a huge fan is required. 2) Embedded CPUs do not have sufficient performance for processing multiple robot tasks that mix AI and non-AI tasks in real-time. To solve these issues, we propose a power-efficient AI-MPU (microprocessor unit) including: 1) a flexible pruning rate control (named flexible N:M pruning) technology capable of up to 16$\times$ AI performance acceleration, and 2) a heterogenous architecture for multi-task & real-time robot operation based on the co-operation among a dynamically reconfigurable processor (DRP), AI accelerator (DRP-AI) and embedded CPU.

This paper discusses a new signal transmission mode that electrically eliminates vertical interconnects, which makes a conventional, standard 400-μm core Flip Chip Ball Grid Array (FCBGA) suitable to millimeter-wave device packaging. The designed FCBGA package has successfully showed a 1dB bandwidth of 90GHz including PCB signal line loss. Additionally, when designed with a thinner substrate, the bandwidth has exceeded 100GHz.

Phase locked loops (PLLs) are utilized in SoCs for automotive industry. In the industry, the system handles with satellite signals which are weak radio waves coming from space. Therefore, the output frequency of PLLs is carefully designed to avoid Electromagnetic Interference (EMI). Recently, Global Navigation Satellite System (GNSS) is becoming more common and available frequency bands for clocks are getting narrow (Fig. 1 (a)). That leads, in many products, replacement integer-N PLLs (Int-N PLLs) with fractional-N PLLs (Frac-N PLLs) is needed to obtain smaller output frequency steps than reference frequency. It is important to make Frac-N PLLs as soon as possible to meet a market opportunity. However, it takes long time to make them from scratch. One of answers would be Frac-N digital PLL whose most part is digital circuit which is quickly designed with RTL. However, most of them need time-to-digital converters (TDCs) to make phase quantization noise small [1], [2]. The TDC is a key analog block that requires long time to design and calibration which increases complexity. If we have a fractional divider (FDIV) to make a Frac-N PLL by just connecting to an Int-N PLL, it is useful. Some Frac-N PLLs [3], [4] have been published and they have FDIVs. In [3], extra coarse frequency control is needed to generate the frequency information, increasing complexity. In [4], two-step phase interpolation has been proposed to reduce $\Delta \sum$ quantization noise. However, one of phase interpolators (PIs) is put together with the phase detector. It is tough to apply this structure to ordinary PLLs.

On-chip ESD current sensor to capture 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> /2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> peak current waveform of system-level ESD injected into IC in high voltage BiCD technology is proposed. Measurement error due to voltage overshoot of high voltage ESD diode is corrected. The sensor would be a key component for avoiding IC destruction or malfunction by system-level ESD.

Bilinear pairing is the fundamental component of practical advanced cryptography. Cost-saving and security-conscious paring coprocessors are required in resource-constrained IoT (Internet-of-Things) devices. Security and cost have basically trade-off relationship. This paper proposes a cost -security-balanced pairing coprocessor for SoC (System on a Chip)-scale devices. Our proposed coprocessor's key point is that the coprocessor computes pairing in affine coordinates instead of projective coordinates that are used in many related studies. The evaluation results show that our proposed coprocessor is approximately 12 percent efficient in area-cycle product (ACP) compared to the current mainstream pairing computation in projective coordinates.