STMicroelectronics (India)

Photonic integrated devices are progressively evolving beyond passive components into fully programmable systems, notably driven by the progress in chalcogenide phase-change materials (PCMs) for non-volatile reconfigurable nanophotonics. However, the stochastic nature of their crystal grain formation results in strong spatial and temporal crystalline inhomogeneities. Here, the concept of spatially-controlled planar guided crystallization is proposed, a novel method for programming the growth of optically homogeneous low-loss Sb2S3 PCM, leveraging the seeded directional and progressive crystallization within confined channels. This guided crystallization method is experimentally shown to circumvent the current limitations of conventional PCM-based nanophotonic devices, including a multilevel non-volatile optical phase-shifter exploiting a silicon nitride-based Mach-Zehnder interferometer, and a programmable metasurface with spectrally reconfigurable bound state in the continuum. Precisely controlling the growth of PCMs to ensure optically uniform crystalline properties across devices is the cornerstone for the industrial development of non-volatile reconfigurable photonic integratedcircuits.

Bonding technologies in heterogeneous wafer integration packaging processes requires defect identification methods beyond the capabilities of the standard ultrasonic defect inspection methods. In the present study, a special infrared defect inspection method with optional stress sensitive mode is discussed for void inspection. Artificial and unintentionally generated process induced voids were identified and qualitatively characterized in non-metallized bonded wafer. Additionally, process induced voids were also revealed in highly metallized device wafers and void position were correlated with that of observed in scanning acoustic microscopy. Stress imaging mode of the infrared method opened up an alternative characterization of defects based on their localized stress lobes.

Advancements in high-speed wireline and wireless applications are driving the demand for high-performance frequency synthesizers. The conventional sub-sampling phase detector (SSPD) suffers from poor reference spur performance, limiting the overall effectiveness of the sub-sampling phase-locked loop (SSPLL). This article presents a SSPLL incorporating a double-balanced sampling mixer-adopted SSPD (DBSMA-SSPD). The proposed design improves the reference spur by reducing reference feedthrough without requiring external calibration or RC networks. A dual-edge sampling technique is introduced to further enhance in-band phase noise performance. The proposed SSPLL employs an LC-voltage controlled oscillator (VCO) as its core to generate a 2.688 GHz frequency. The design is implemented and fabricated using an industrial 65-nm CMOS process, occupying a total active area of 0.39 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The SSPLL successfully locks to a 2.688 GHz frequency from a reference frequency of 168 MHz, consuming around 4.1 mW from a 1.2-V supply. The design demonstrates state-of-the-art performance, achieving a measured rms jitter of 207.7 fs over an integration bandwidth of 10 kHz–100 MHz and a measured reference spur of −72 dBc, attributed to the proposed DBSMA-SSPD. Additionally, it achieves an in-band phase noise of −122.16 dBc/Hz at a 200-kHz frequency offset, with a jitter-power figure-of-merit (FOM) of −247.5 dB.

Not much literature is available on the design and implementation of a high power (>5kW) high density solar MPPT converter (either buck or boost) targeting the 200-850V range and with multi-level topology, to target ~850VDC. This paper illustrates a 10kW MPPT controller implemented with SiC 650V MOSFETs but in a three-level flying capacitor configuration and it targets an input voltage of 425-850V with an output of 400V nominal. There are two independent channels with active current sharing on the common output 400V DC bus for feeding the battery bank or an inverter. The peak power conversion efficiency of the system exceeds 98.5% and a standard Perturb and Observe algorithm is used for the MPPT function. One single 32-bit STM32G4 ARM MCU controls all the functions of MPPT, Buck conversion of two channels, flying capacitor balancing of two channels, output regulation and protection. It is targeted at renewables and energy storage applications.

A peak-current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PK</inf>) limited Pulse-Frequency Modulation (PFM)-based SoC-compatible buck converter is designed in scaled-CMOS technology. In an Li-ion compatible input supply range of 2.7V-4.2V, it delivers a 0.55V output. It employs a low-power Bandgap reference, in-built push-pull voltage-regulators with adaptive-biasing, duty-cycled sensors and a failsafe asynchronous block. This architecture alleviates the need for a clock and limits inrush current at startup. Made using 3.3V bulk-MOSFETs, device voltage stress is managed for each sub-block. It only needs external L & C of 4.7µH & 4.7µF. Occupying an area of 660µm x 1465µm, it targets Standby mode of operation for low-power applications like Internet-of-Things (IoT) and Bluetooth Low Energy (BLE), supporting a load-current of 0.5mA to 10mA with >80% efficiency and has >70% efficiency till 0.1mA. It achieves a peak efficiency of 84.7% at 5mA load.