Siemens (Singapore)

CA19-9 is elevated in pancreatic cancer and other malignancies, and commonly used in clinical practice. Unfortunately, CA19-9 immunoassays are not harmonized, and reference intervals may differ between assays. The aim of this study was to establish the reference interval of the ADVIA Centaur/Atellica IM CA19-9 assay in an apparently healthy Singapore adult population. This is a retrospective cross-sectional study. De-identified data from Health Screening participants were extracted from our database. Subjects with biochemical results suggesting anaemia, diabetes mellitus, viral hepatitis or abnormal liver, and renal and tumour markers were excluded. Outlier and subclass analyses by age and sex were performed. CA19-9 reference limits and 90% confidence intervals were then determined for candidate subclasses. Data from 12,174 subjects (5846 males and 6328 females) were available after exclusion criteria were applied. CA19-9 results did not follow a normal distribution and were higher in females compared to males (P < .001). Although CA19-9 means were statistically different between certain age groups, the evaluable 99th percentile reference limits were not statistically different. The overall 99th percentile reference limits for the Centaur/Atellica CA19-9 assay was 37 U/mL for males 21-80years, and 60U/mL for females 21-80years. Our results suggest that separate CA19-9 reference intervals should be applied for males and females.

This paper is focused on the digital twin solution to validate the performance optimization of production lines. We propose three steps to approach the digital twin for production lines. As the first step, a simulation model is created to imitate real world behavior. After that, automation engineering is applied to communicate between real world and virtual model. A programmable logic controller (PLC) code is embedded as a communication language. Digital twin realization is shown by integration of simulation and automation. A case study presents how to bring practical benefits by applying the digital twin solution in production line virtual commissioning.

The most important reason for the lack of commercial residue arithmetic (RA) based systems is not the slow and area consuming reverse conversion, but the absence of research that explores the system-level trade-offs of such arithmetic in actual VLSI implementations. Such system-level issues are-choice of the moduli set, effect of moduli imbalance on resulting VLSI implementation, choice of the reverse and forward convertors, use of lookup versus computation for modular operations, system characteristics that indicate RA suitability and finally, typical VLSI area and performance figures. This paper explains these concerns by presenting novel RA architectures for VLSI correlators employed in radioastronomy and ultrasonic blood flow measurement. A state-of-the-art, high performance (80-100 MHz), RA-based correlator ASIC was successfully fabricated as a result of this research.

This paper presents a nuanced robustness analysis for structures when only limited information is available. A new methodology based on fuzzy set theory is proposed to cope with scarce information as a major problem in the performance assessment of existing structures. The developed robustness measure provides information on the relationship between structural robustness and the magnitude of uncertainty in the damage of the structure. This feature is enabled through a nuanced consideration of imprecision in the damage assessment through alpha-level discretization. An entropy-based robustness measure is formulated as a function of imprecision in the damage state. On this basis, different design solutions can be compared in a one-swoop analysis with respect to their robustness for different magnitudes of damage. Furthermore, this approach can be used to assess the effort for inspection versus gain in precision of the predicted structural performance. The development is of a general nature. In this paper, it is elucidated in the context of a typical offshore engineering problem to demonstrate its application in practical cases. Fixed offshore platforms with different brace configurations are compared in light of robustness with respect to damage from corrosion.

The ability to accurately predict traffic speed in a large and heterogeneous road network has many useful applications, such as route guidance and congestion avoidance. In principle, data-driven methods, such as support vector regression (SVR), can predict traffic with high accuracy because traffic tends to exhibit regular patterns over time. However, in practice, the prediction performance can significantly vary across the network and during different time periods. Insight into those spatiotemporal trends can improve the performance of intelligent transportation systems. Traditional prediction error measures, such as the mean absolute percentage error, provide information about the individual links in the network but do not capture global trends. We propose unsupervised learning methods, such as k-means clustering, principal component analysis, and self-organizing maps, to mine spatiotemporal performance trends at the network level and for individual links. We perform prediction for a large interconnected road network and for multiple prediction horizons with an SVR-based algorithm. We show the effectiveness of the proposed performance analysis methods by applying them to the prediction data of the SVR.

Cardiac multi-detector-row computed tomography (MDCT) angiography has shown high levels of sensitivity and especially negative predictive value regarding the diagnosis of coronary artery disease (CAD). This study was designed to determine the value of a 64-slice-MDCT scanner in comparison to invasive coronary angiography for the detection of CAD in a population of symptomatic patients. Fifty-one patients with suspected CAD underwent conventional coronary angiography and ECG-gated cardiac 64-slice-MDCT angiography with a rotation time of 330 ms, a collimation of 64x0.6 mm and a slice thickness of 0.75 mm. Blinded patient- and segment-based analysis was performed for the detection of stenoses >or=70% of the vessel lumen. 95% of all coronary segments were assessable by MDCT angiography. Patient-based (segment-based) analysis revealed a sensitivity of 97.8% (86.7%), specificity of 50% (95.2%), positive predictive value of 93.6% (75.2%) and negative predictive value of 75% (97.7%). Inter-rater agreement revealed a kappa-value of 0.558 (0.722). In this symptomatic patient group a 64-slice-MDCT scanner shows good agreement on a segment-based analysis but only moderate agreement on a patient-based analysis. The diagnostic accuracy of 64-slice-MDCT coronary angiography is negatively influenced by the high pre-test probability of this symptomatic patient collective.

In the paper, we investigate and evaluate a radio resource allocation strategy for non-realtime data services in a single cell UMTS uplink. We focus on a packet level allocation strategy, which guarantees certain fairness levels. Non-realtime data services normally have average throughput requirement, which can be achieved either by way of continuous transmission with a low instantaneous data rate or by way of a higher instantaneous data rate over a shorter time. We find that it is energy-efficient by transmitting with high instantaneous data rate based on variable spreading factor operation. Furthermore, based on an average throughput based fairness criterion, we propose a fair resource allocation scheme that is easy to implement. Simulations are used to evaluate the proposed scheme.

This technique detects all active pins in a test pattern electrically using an ATE system. Exhaustive checks on signal pins with different input and output levels ensures that all patterns are stable. Information gathered on active pins for all patterns allows optimised pattern selection for level testing. The technique is portable across different ATE systems and devices. Results show that the test time can be reduced, by up to 31.1% with the proper selection of patterns for level tests of VLSI devices.

Recent trends like increasing operating frequencies, larger die sizes and demand for greater portability make power reduction a hard taskmaster. It is acknowledged that the greatest returns come from optimization at the architectural and technology level. We present, for the first time, residue architectures that reduce the power by more than 70% without changes in technology. This reduction is achieved without sacrificing performance and with minimal sacrifice in area (less than 60%). The key to such low power solutions is trading-off the speed gained by parallelism for lower power. Existing proposals that achieve similar trade-offs demand an area increase of more than a factor of two and also increased control complexity. Other benefits of using residue arithmetic for low power is the significant reduction in peak current and increased design locality. The role of the number of computations per forward (or reverse) conversion in determining the power characteristics of the system are also analyzed and explained. The effectiveness of the methodology is illustrated using a system that extracts a 256-point FFT of the input signal.