- Research Article
- 10.1109/tvlsi.2025.3649063
Fast Modular Reduction Algorithm and Reconfigurable Domain-Specific Architecture Design Based on Generalized Mersenne Primes
- Jan 01, 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Xinyu Wang + 7 more +7
Modular arithmetic enjoys a broad spectrum of applications. In recent years, the advancement of post-quantum cryptography (PQC) has imposed growing demands on the flexibility and scalability of domain-specific accelerators. This article presents a fast modular reduction algorithm based on generalized Mersenne (GM) primes, which employs approximate scaling and iterative compression approaches to rapidly converge the quotient value while reducing the precomputation complexity to rely solely on the modulus itself. Building upon this algorithm, we have designed a reconfigurable modular reduction array using multiplier units with smaller word length. Operating at 1GHz, the proposed array achieves an area reduction of 45.14% compared to Barrett-based structures, and 13.93% compared to Montgomery-based structures. The array has been integrated into a complete number-theoretic transform (NTT) acceleration architecture. The resulting reconfigurable GM/general modular reduction domain-specific architecture elevates the chip frequency to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.42\sim 1$</tex-math> </inline-formula> GHz under the same process technology. Under identical test conditions, it improves area efficiency by 10.6% and reduces energy consumption by 17.0% compared to the state-of-the-art ASIC design. When compared to the latest field-programmable gate array (FPGA) implementations, it achieves a reduction in area-time product (ATP) by 7.2%~18.4% for Kyber and by 13.4% for Dilithium. These results strongly demonstrate the notable advantages of the hardware-friendly GM algorithm.
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