Synopsys (Switzerland)

MOTIVATION Longitudinal molecular studies of the mouse brain are limited by the need for terminal tissue collection. This prevents analysis of preexisting molecular states and their evolution within the same individual. We developed a stereotactic microbiopsy technique that enables minimally invasive sampling of defined brain regions in vivo . The method preserves survival while yielding material suitable for RNA and nuclei isolation. It provides a practical solution for linking baseline molecular states to subsequent behavioural, pharmacological, or disease-related outcomes. SUMMARY This study presents a stereotactic microbiopsy technique for sampling defined brain regions in living mice, enabling transcriptomic and epigenomic analyses without sacrificing the animal. The method will allow pre-intervention tissue collection, making it possible to separate preexisting molecular differences from experience- or treatment-induced changes. We show that microbiopsies yield sufficient, high-quality RNA and chromatin for sequencing, with minimal tissue damage that largely resolves over time. The procedure uses standard stereotactic equipment and achieves reproducible spatial precision when the syringe is stabilised. This approach provides a practical framework for within-subject molecular comparisons, reducing animal use and enabling longitudinal profiling of the living mouse brain. It establishes a foundation for investigating how baseline molecular states influence later physiological or behavioural outcomes.

This paper presents the design, implementation, and performance evaluation of a Common-Emitter-based Cascode Low Noise Amplifier (LNA) targeted at 300 GHz operation in 130nm SiGe BiCMOS SG13G2 technology platform. Pushing silicon-based front-end electronics into the sub-terahertz (sub-THz) regime demands careful co-optimization of device selection, noise-matching, stability management, and high-frequency passive integration. The designed LNA employs a common-emitter (CE) input device stacked with a double cascode transistor to suppress the Miller effect, enhance reverse isolation, and increase gain while maintaining low noise. Wideband input matching is achieved through on-chip transmission-line and metal-insulator-metal (MIM) capacitive networks that absorb device parasitics at G-band/300 GHz frequency. Input return loss better than -10 dB across band, unconditional stability (Rollet K > 1) over 200–350 GHz, and dc power consumption of 92 mW from a 3.7 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V$</tex> power supply. A comparison with recent state-of-the-art SiGe, CMOS, and III-V LNAs operating above 200 GHz highlights the competitiveness of the presented approach in terms of gain/noise trade-off and integration density. The 3 dB bandwidth of the CE LNA are 58.5 GHz and 41 GHz without and with the base parasitic inductor of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L_{par}=9$</tex> pH. Peak power gain of the LNA is 33.834 dB at 291 GHz with base parasitic inductor of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L_{par}=9$</tex> pH. Peak power gain of the LNA is 21.89 dB at 293 GHz without base parasitic inductor. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{1-dB}$</tex> compression point of the LNA is -30 dBm and IIP3 of the LNA is -17 dBm.

Hybrid metal printing technologies, such as StarJet, offer a non-contact approach for the direct deposition of molten metals, enabling a wide range of applications, including high-resolution PCB interconnection, flexible electronics on polymer substrates, and localized soldering of electronic components on thermally sensitive materials. These advanced manufacturing techniques rely on the precise ejection and impact of micrometer-scale molten droplets at elevated temperatures, where fluid dynamics, heat transfer, and phase change phenomena are tightly coupled. In this study, we numerically investigate the behavior of droplets of a tin-silver-copper alloy impacting solid surfaces. The model is based on the Navier-Stokes equations coupled with heat transfer and phase change, incorporating temperature-dependent thermophysical properties to accurately capture both spreading and solidification stages. The droplets have diameters of approximately 400 µm and impact the substrate at high velocities, leading to characteristic timescales on the order of milliseconds. High-speed camera measurements were conducted to validate the droplet dynamics, while the lack of thermal imaging posed challenges in assessing the temperature field during impact. Despite this, the simulations yield valuable insights into the transient interaction between hydrodynamic and thermal effects, supporting the development and optimization of hybrid metal printing strategies.

This paper presents a simulation-based approach for evaluating Electro Magnetic Interference (EMI) in a power supply PCB using Ansys toolsets for automotive applications. The methodology spans multiple levels of abstraction, beginning with circuit-level simulations to assess functional voltage behavior. This is followed by PCB-level EMI analysis using computational electromagnetic solvers to characterize Radiated and Conducted Emissions (RE and CE). Finally, component-level simulations are performed, incorporating critical elements such as the antenna, test bench, cable harness, Line Impedance Stabilization Network (LISN), and surrounding test environment, in compliance with the CISPR 25 standard. Comparative analysis highlights the tradeoffs in simulation fidelity, complexity, and computational efficiency across the three levels. Results demonstrate how earlystage EMI evaluation can enhance design robustness while reducing the need for multiple hardware prototypes.

In electric and hybrid vehicles, the traction inverter converts DC power from the high-voltage battery to AC power for the motor. This process generates heat due to joule heating, raising component temperatures. To ensure efficiency and longevity, temperatures must remain within safe limits with good thermal uniformity to minimize stress. Faulty designs or uneven loads can exceed these limits, causing thermal failure, derating and mechanical damage. Thus, inverter systems must dissipate heat effectively to maintain safe operation. This paper describes numerical simulation of a traction inverter aiming to improve heat dissipation and reduce temperature. Designed per OEM requirements, the inverter is compact and lightweight while meeting performance criteria. Simulations using 3D Computational Fluid Dynamics (CFD) predicted overheated components and non-uniform temperature distribution. The inverter was then redesigned with a unified coolant system linking components, enabling effective heat removal and lowering temperatures below safe limits. This redesign of the coolant channel demonstrates significant improvements in thermal management and reliability for electric vehicle inverter systems.

Latch-up [1] remains a critical reliability concern in advanced CMOS technologies, particularly in high-voltage General-Purpose Input/Output (GPIO) circuits that serve as the interface between SoCs and external systems. The latch-up issues are quite prevalent in adjacent N-wells, which are biased by different voltage supplies. This issue gets compounded in Fail-safe I/Os due to possible grounding of the N-well which creates higher voltage than V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</inf> (holding voltage) of the parasitic SCR. Conventional latch-up prevention techniques such as wide guard rings [2], [3] and large well spacing guarantee robustness but significantly increase the I/O ring area, which is a major limitation in highly integrated 7nm system-on-chip (SoC) designs. Higher operating voltage rating becomes more demanding in terms of spacing requirement to achieve higher holding voltage leading to very high area penalty. A novel architecture to implement the driver section layout is presented in this paper, that automatically takes care of the latch-up spacing for adjacent N-wells present in different biasing domains and can help in area saving by approximately 30-40% of total IP area compared and enables customers to achieve 30-40% higher I/O pad density without using extra cost layers like Deep-NWELL.

Modern high-speed SerDes and clock/data recovery (CDR) systems heavily rely on phase interpolators (PI) to generate accurate clocks for timing critical paths. As data rates continue to scale, achieving linear code-to-phase transfer becomes increasingly difficult due to device nonidealities, shrinking supply voltages, and tighter jitter budgets. Nonlinearity in the interpolator directly degrades timing accuracy, leading to higher bit-error rates (BER). This work explores methods to improve interpolator linearity in CMOS inverter-based mixer architectures. The three methods are: digital predisposition, an ac-coupled feedback inverter at the input, and reduced supply operation of the mixer stage. Simulation results show that the combination of these methods effectively flattens the code-to-phrase characteristics and reduces integral nonlinearity. Trade-offs are added circuit complexity, area and jitter. The results demonstrate that with modest design, the proposed methods provide a practical way toward more accurate PIs in advanced SerDes and CDR applications.

Developing high-stakes autonomous systems that include Artificial Intelligence (AI) components is complex; the consequences of errors can be catastrophic, yet it is challenging to plan for all operational cases. In stressful scenarios for the human operator, such as short decision-making timescales, the risk of failures is exacerbated. A lack of understanding of AI failure modes obstructs this and so blocks the robust implementation of applications of AI in smart systems. This prevents early risk identification, leading to increased time, risk and cost of projects. A key tenet of Systems Engineering and acquisition engineering is centred around a "left-shift" in test and evaluation activities to earlier in the system lifecycle, to allow for "accelerated delivery of [systems] that work". We argue it is therefore essential that this shift includes the analysis of AI failure cases as part of the design stages of the system life cycle. Our proposed framework enables the early characterisation of risks emerging from human-autonomy teaming (HAT) in operational contexts. The cornerstone of this is a new analysis of AI failure modes, built on the seminal modelling of human-autonomy teams laid out by LaMonica et al., 2022. Using the analysis of the interactions between human and autonomous systems and exploring the failure modes within each aspect, our approach provides a way to systematically identify human-AI interactions risks across the operational domain of the system of interest. The understanding of the emergent behaviour enables increased robustness of the system, for which the analysis should be undertaken over the whole scope of its operational design domain. This approach is illustrated through an example use case for an AI assistant supporting a Command & Control (C2) System.

Abstract A finite element-based simulation framework was proposed to analyze fatigue crack growth in metallic parts. This framework allows for automatic crack extension and remeshing for complex crack shapes. The accuracy of the simulation method was validated using available experimental data. In the simulation model, an initial elliptical shaped crack was created according to the test setup, and the tabular fatigue crack growth law was adopted based on the provided data. The loading cycles presented in the test were represented by a cycle-by-cycle loading scheme, which accounted for the different number of sub-cycles, applied load, and R ratio within each loading block. The simulated crack increments and crack shapes at various accumulated cycles were compared with the fractographic results. It was observed that the crack size and shape predictions by the finite element model aligned well with the experimental data. The influence of the different fatigue crack growth laws on simulated crack growth was examined and found to be significant. To address the higher crack growth rate at larger accumulated cycles predicted by the model, a crack closure function was implemented. It was determined that plasticity-induced crack closure could be a plausible cause for the discrepancy between simulation and test results at higher accumulated cycles.