Texas Instruments (France)

The periodontal morphotype is a leading feature to be born in mind during surgical, implant, prosthetic, restorative as well as orthodontic treatment. A fragile morphotype will rapidly trigger severe and worrying clinical repercussions for the patient. In order to minimize the risks involved, sound knowledge of the different morphotypes and of the techniques for clinically evaluating them is a major requirement. These factors need to be regularly reassessed since morphotypes can vary throughout the course of treatment. Detecting and controlling mucogingival risk factors will enable an appropriate clinical approach designed to avoid the onset of secondary recessions or other gingival pathologies.

Yield estimation is an indispensable piece of information at the onset of high-volume production of a device. It can be used to refine the process/design in time so as to guarantee high production yield. In the case of migration of production of a specific device from a source fab to a target fab, yield estimation in the target fab can be accelerated by employing information from the source fab, assuming that the process parameter distributions in the two fabs are similar, but not necessarily the same. In this paper, we employ the Bayesian Model Fusion (BMF) technique for efficient yield prediction of a device in the target fab. BMF adopts prior knowledge from the source fab and combines it intelligently with information from a limited number of early silicon wafers from the target fab. Thus, BMF allows us to obtain quick and accurate yield estimates at the onset of production in the target fab. The proposed methodology is demonstrated on an industrial RF transceiver.

The majority of applications, ranging from the low complexity to very multifaceted entities requiring dedicated hardware accelerators, are very well suited for Multiprocessor Systems-on-Chips (MPSoCs). It is critical to understand the general characteristics of a given embedded application: its behavior and its requirements in terms of MPSoC resources. This paper presents a complete method to study the important aspect of memory characteristic of an application. This method spans the theoretical, architecture-independent memory characterization to the quasi optimal static memory allocation of an application on a real shared-memory MPSoCs. The application is modeled as an Synchronous Dataflow (SDF) graph which is used to derive a Memory Exclusion Graph (MEG) essential for the analysis and allocation techniques. Practical considerations, such as cache coherence and memory broadcasting, are extensively treated. Memory footprint optimization is demonstrated using the example of a stereo matching algorithm from the computer vision domain. Experimental results show a reduction of the memory footprint by up to 43 % compared to a state-of-the-art minimization technique, a throughput improvement of 33 % over dynamic allocation, and the introduction of a tradeoff between multicore scheduling flexibility and memory footprint.

Embedded real-time applications in communication systems have significant timing constraints, thus requiring multiple computation units. Manually exploring the potential parallelism of an application deployed on multicore architectures is greatly time-consuming. This paper presents an open-source Eclipse-based framework which aims to facilitate the exploration and development processes in this context. The framework includes a generic graph editor (Graphiti), a graph transformation library (SDF4J) and an automatic mapper/scheduler tool with simulation and code generation capabilities (PREESM). The input of the framework is composed of a scenario description and two graphs, one graph describes an algorithm and the second graph describes an architecture. The rapid prototyping results of a 3GPP Long-Term Evolution (LTE) algorithm on a multicore digital signal processor illustrate both the features and the capabilities of this framework.

Abstract In order to protect a cryptographic algorithm against Power Analysis attacks, a well-known method consists in hiding all the internal data with randomly chosen masks.Following this idea, an AES implementation can be protected against Differential Power Analysis (DPA) by the “Transformed Masking Method”, proposed by Akkar and Giraud at CHES’2001, requiring two distinct masks. At CHES’2002, Trichina, De Seta and Germani suggested the use of a single mask to improve the performances of the protected implementation. We show here that their countermeasure can still be defeated by usual first-order DPA techniques.In another direction, Akkar and Goubin introduced at FSE’2003 a new countermeasure for protecting secret-key cryptographic algorithms against high-order differential power analysis (HO-DPA). As particular case, the “Unique Masking Method” is particularly well suited to the protection of DES implementations. However, we prove in this paper that this method is not sufficient, by exhibiting a (first-order) enhanced differential power analysis attack. We also show how to avoid this new attack.KeywordsTamper-resistant devicesSide-Channel attacksPower AnalysisDPATransformed Masking MethodUnique Masking MethodDESAES

This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed set of blocks takes into account most of the SC /spl Sigma//spl Delta/ modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC /spl Sigma//spl Delta/ modulator.

We propose a complete methodology for the automatic generation of test cases in the context of digital circuit validation. Our approach is based on a software model of the system to verify in which some modules are written in the Esterel language. An initial test suite is simulated and the state coverage is computed. New test sequences are automatically generated to reach the missing states. We then convert those sequences into system-level test cases (i.e. instruction sequences) by a technique called pipeline inversion. The method has been applied for the functional validation of an industrial DSP system giving promising results.

This paper describes a new methodology allowing one to increase the efficiency of functional validation. The approach is based on a combination of simulation and formal techniques. It consists of first building formal models of digital hardware modules. The coverage of a test suite can then be accurately measured and new test cases are automatically generated to increase the coverage. This methodology has been applied during the development of a commercial DSP system. It has shown that, in spite of a very large test suite consisting of 300 million simulation cycles, there was still room for coverage improvement.

Localized electrical contact phenomena during wafer test can significantly affect contact resistance magnitude and stability of tungsten (W), tungsten-rhenium (WRe), beryllium-copper (BeCu), Pd-alloy (Paliney-7), and metallic-alloy (NewTek-Probe) probes. Typically, increased and unstable contact resistance (C/sub RES/) during aluminum wafer test at 85/spl deg/C with tungsten (W) and tungsten-rhenium (WRe) probe needles is attributed to adherent oxides from the aluminum bond pads. New experimental data indicates that oxide formation due to localized Joule heating at the probe tip contact "a-Spots" significantly contributes to the C/sub RES/ variations. Use of non-oxidizing probe materials could provide low and stable C/sub RES/ with reduced cleaning frequency at elevated temperatures. Preliminary production level beta testing on actual devices using NewTek probes demonstrated significant reductions in continuity failures, cleaning frequency, and operator intervention.

A ninth-order recursive digital filter with a 47.6MHz clock rate/ 23.8 MHz sample rate has been designed and fabricated on a single chip using a 1.2pm CMOS technology. The filter achieves an attenuation of 73dB with a transition width of only 5% of the sample rate. The chip demonstrates architecture and circuit design techniques for sharp roll-off required in high date-rate communication systems.