동적 분기 예측을 지원하는 임베디드 코어 자동 생성 시스템의 설계와 구현

To achieve highly accurate branch prediction, it is necessary not only to allocate more resources to branch prediction hardware but also to improve the understanding of branch execution characteristics. In this paper, we present a new profile-based conditional branch analysis technique called branch working set analysis to provide additional information about control flow behavior of general purpose applications. This analysis evaluates the dynamic behavior of branch execution by partitioning either individual branches or pre-classified branch groups into sets based on temporal locality and ordering information. We refer to these sets as the working sets of branches. To demonstrate the usefulness of this form of analysis, we examine the efficiency of current allocation techniques for branch history table (BHT) space and propose a new solution to this allocation process that improves the performance of these tables. In our approach the mapping between branch instructions and BHT entries is specified during compilation to reduce table contention-leading to more relevant histories and improved predictor performance. As a result, even for programs with a large number of static branches, only 100 to 200 history entries are needed to approximate the performance of larger 1024-entry BHT. Furthermore, when the technique is applied to a predictor with 1024-entry BHT its prediction accuracy is improved by 16%-comparable with the performance of a BHT of infinite capacity.

Dynamic branch prediction in the high-performance processors was a specific instance of a general time series prediction problem that occurred in many areas of science. In contrast, most branch prediction research focused on dynamic two-level branch prediction techniques, a very specific solution to the branch prediction problem. In this paper, we introduced a kind architecture of loop detector and b-cache pipeline restorer which were based on GAs dynamic two-level branch prediction. The processors which brought the extend architecture can reduce redundancy decode of program that contained lots of loop branch instructions and reduce the resume time of stall pipeline by the miss prediction.

When CPU enters the era of instruction level parallelism, the execution cycle of instructions has become shorter and shorter. Meanwhile, the processing speed of CPU has become faster and faster. However, only from the execution process of CPU instructions, there is a key factor that limits the speed of CPU processing instructions, namely, the branch instruction processing. The branch predictor is used to predict the execution result of the current branch instruction (taken/non-taken), which can make the program counter get the target instruction to continue to execute according to the prediction result before calculating the target jump address. If the prediction is correct, it will greatly improve the execution efficiency of CPU. This paper starts from the two basic categories of static branch prediction and dynamic branch prediction. Then analyse their prediction principle, prediction accuracy and component consumption used for prediction. For static branch predictor, its hardware consumption is less than that of dynamic branch predictor, and its accuracy is also lower than that of dynamic branch predictor. Moreover, their shortcomings are pointed out in this paper. At last, based on the original branch predictor, better branch predictors developed in recent years are introduced. In the future, considering the hardware consumption, I think the development of branch predictor will continue to optimize the branch predictor combining global history and local history, from the number of stored entries, the correlation between branch instructions and so on. On the premise of executing a large number of instructions, every little improvement in the efficiency of the predictor will bring huge benefits.

The need for modern processors is based on fast and precise branch predictors to improve the execution of instructions in the pipeline. In a parallel processor, the pipeline cannot execute the conditional instructions with the next clock cycle, leading to a pipeline stall. To address this issue, this paper suggests a variety of branch prediction techniques for improving the execution speed of conditional instructions. Firstly, a simple branch prediction and a dynamic branch prediction are applied to the trace files using saturating counters. Among these two, dynamic branch prediction provides better results by enhancing the accuracy rate of 2.01% than the static branch prediction. Further, the perceptron branch predictor predicts the implementation by using a table of perceptron and train function. This prediction scheme reduces the difficulties in dynamic branch predictor schemes such as reduces the complexity in history length table and improves the accuracy rate by 5.36%. For accuracy, a novel model based on global perceptron branch predictor is developed, which uses both global and per branch information. Trace-driven simulations have been performed by varying the range of hardware budget, traces file size, and the length of history register to increase the accuracy rate of each branch prediction technique. The obtained results suggest that the proposed global perceptron branch predictor provides an increased accuracy rate of 10.47% at 4 kb hardware budget and 8.06% at 4-bit history length than the perceptron branch predictor.

Dynamic branch prediction in high-performance processors is a specific instance of a general time series prediction problem that occurs in many areas of science. In contrast, most branch prediction research focuses on two-level adaptive branch prediction techniques, a very specific solution to the branch prediction problem. An alternative approach is to look to other application areas and fields for novel solutions to the problem. In this paper, we examine the application of neural networks to dynamic branch prediction. Two neural networks are considered: a lecturing vector quantisation (LVQ) Network and a backpropagation network. We demonstrate that a neural predictor can achieve misprediction rates comparable to conventional two-level adaptive predictors and suggest that neural predictors merit further investigation.

We have designed a DLX-based superscalar processor simulator. This simulator provides many more functions than its predecessors developed elsewhere. We have added trap handlers and required C functions in the system so that most of the SPEC92 programs now run on the simulator. In addition, this simulator is fully configurable and re-configurable. Specifically, the following options and functions are provided by the simulator.• Central window versus distributed reservation stations.• Branch prediction mechanisms using static or dynamic schemes. The later provides branch target buffer and branch history table.• Configurable functional units.• A fully configurable KNL non-blocking cache structure incorporated int he simulator. (K: the number of ways. N: the number of cache lines in a way. L: line size). Split versus unified option and cm + βmL/D memory latency model.• Better debugging functions allowing the interruption of the simulation, reconfiguration, restart in a cycle-by-cycle fashion, or run to the end.• NT/Win95 platform ready.This DLX-based superscalar simulator is instruction-driven, which offers richer educational features than most of the trace-driven simulators. For information about this simulator, please refer to http://com.el.yuntech.edu.tw.

Designing a modern microprocessor is a complex task that demands careful balance between cycle time, cycle-per-instruction and area costs. In particular, the instruction fetch unit greatly affects the performance of a multi-issue processor. It must provide adequate bandwidth to sustain peak instruction issue rate and must predict future instruction sequences with high accuracy. In the UltraSPARC prefetch and dispatch unit design, we examined a technique that combined two prediction methods: predictive set-associative cache and in-cache prediction. This combination was compared with alternative designs such as direct-mapped and set-associative caches, and a branch history table and a branch target buffer. We chose the combined prediction technique for its fast cycle time, lower cycle-per-instruction, and lower area costs. This paper summarizes the trade-off decisions made in the design of the UltraSPARC instruction prefetch and dispatch unit.

This paper investigates how dynamic branch prediction in a microprocessor affects the predictability of execution time for software running on that processor. By means of experiments on a number of real processors employing various forms of branch prediction, we evaluate the impact of branch predictors on execution time predictability. The results indicate that dynamic branch predictors give a high and hard-to-predict variation in the execution time of even very simple loops, and that the execution time effects of branch mispredictions can be very large relative to the execution time of regular instructions. We have observed some cases where executing more iterations of a loop actually take less time than executing fewer iterations, due to the effect of dynamic branch predictors. We conclude that current dynamic branch predictions schemes are not suitable for use in real-time systems where execution time predictability is desired.

We evaluate the effects of guarded (or conditional, or predicated) execution on the performance of an instruction level parallel processor employing dynamic branch prediction. First, we assess the utility of guarded execution, both qualitatively and quantitatively, using a variety of application programs. Our assessment shows that guarded execution significantly increases the opportunities, for both compiler and dynamic hardware, to extract and exploit parallelism. However, existing methods of specifying guarded execution have several drawbacks that limit its use. Second, we study the interaction of guarded execution and dynamic branch prediction and show that the use of guarded execution significantly increases the number of instructions between mispredicted branches. Third, we propose a new method of specifying guarded execution. The proposed method uses special GUARD instructions, which can be used to incorporate guarded execution into existing instruction sets. GUARD instructions realize the full power of guarded execution, without the drawbacks of existing methods of specifying guarded execution.

Taking dynamic branch prediction into account in WCET determination turns out to be complex, particularly because of the possible interferences between branches. In this paper we argue the case for using static instead of dynamic branch prediction: the aliasing problem is swept away and, in many cases, the estimated worst-case numbers of branch mispredictions are reduced. We propose a method to predict each branch at compile time. Experimental results show how effective this approach can be.

In order to achieve an optimum performance of a given application on a given computer platform, a program developer or compiler must be aware of computer architecture parameters, including those related to branch predictors. Although dynamic branch predictors are designed with the aim of automatically adapting to changes in branch behavior during program execution, code optimizations based on the information about predictor structure can greatly increase overall program performance. Yet, exact predictor implementations are seldom made public, even though processor manuals provide valuable optimization tips.This paper presents an experimental flow with a series of microbenchmarks that determine the organization and size of a branch predictor using on‐chip performance monitoring registers. Such knowledge can be used either for manual code optimization or for design of new, more architecture‐aware compilers. Three examples illustrate how insight into exact branch predictor organization can be directly applied to code optimization. The proposed experimental flow is illustrated with microbenchmarks tuned for Intel Pentium III and Pentium 4 processors, although they can easily be adapted for other architectures. The described approach can also be used during processor design for performance evaluation of various branch predictor organizations and for testing and validation during implementation. Copyright © 2004 John Wiley & Sons, Ltd.

Many aspects of speculative multithreading have been under constant and crucial research in the recent times with the increased importance in exploiting parallelism in single thread applications. One of the important architectural optimizations that is very pertinent in this scenario is branch prediction. Branch Prediction assumes increased importance for multi-threading systems that execute threads speculatively, since wrong predictions can be much costlier here, in terms of threads, than a few instructions that occupy the pipeline in a uni-processor. Conventional branch prediction techniques have provided increasingly better prediction accuracies for uni-core processing. But the branch prediction itself takes on a whole new dimension when applied to multi-core architectures based on Speculative Multithreading. Dependence on global branch history has helped branch predictors to achieve high prediction accuracy in single thread applications. The discontinuity of global history created at the thread boundaries cripple the performance of branch predictors in a multi-threaded environment. Many studies in the past have tried to address the branch history problem to improve the prediction accuracy. Most of these have been found either to be architecture specific or complex in terms of the hardware needed to recreate or approximate the right history to be given to the threads when they start executing out of order. This hardware overhead increases as the number and size of threads increase thereby limiting the scalability of the algorithms proposed so far. The current thesis takes a different direction and proposes a simple and scalable solution to effectively reduce the misprediction rates in Speculative Multithreaded systems. This is accomplished by making use of a synergistic interaction between threads to boost the inherent biased nature of branches and using less complex hardware to reduce aliasing between branches in the threads. The study proposes a new scheme called the Global Broadcast Buffer scheme to effectively reduce branch mispredictions in Speculative Multithreaded architectures.

As fields like AI and robotics continue to expand, the demand for processors that are both powerful and energy-efficient is growing. This imposes the need for the development of such processors at a large scale and at a faster rate, which is possible through open-source development. While the current computing industry is dominated by proprietary technologies and licensed architectures, open-source hardware is rapidly gaining popularity across all industry segments, from high-performance computing to edge-IoT applications.This paper presents the design and FPGA implementation of a 32-bit five-stage pipelined processor core based on the RISC-V open-source Instruction Set Architecture (ISA). The proposed design presents a simple implementation of the RISC-V core, incorporating a 2-bit branch predictor. This makes it easier for beginners to understand the fundamental architecture of a pipelined RISC processor and branch predictors. Additionally, the design has considerable potential for future upgrades. The core is developed using SystemVerilog and has been tested through simulations in Verilator and Xsim, as well as by deploying it on a Basys3 FPGA board.

High-performance superscalar processors, which can be used in building base-stations of cell phones and cloud-based web servers, rely heavily on aggressive branch predictors to avoid stalls no matter the branch is taken or not. Dynamic branch predictor which is based on the historical records of the previously executed branches always outputs good performance. Two-bit predictor discussed in this paper is one of the most popular ones that always practically employed. This paper demonstrates two implementations of two-bit predictors. Using BTB to process solo conditional branches is the first one, which is normally used. Other categories of branch instructions may results in several bubbles as the penalty. While the other implementation employs BTB dealing with all kinds of branch instructions, generating target addresses without any delay cycle. Simulation results show that the second implementation has much better performance than the former one. It decreases the mis-prediction rate from 12.26% to 11.48%, and also has much higher prediction accuracy on indirect jumps. With these results, we have our predictor re-designed accordingly and implemented successfully in superscalar processors.

The design of the modern, enterprise-class IBM z15 branch predictor is described. Implemented as a multi-level look-ahead structure, the branch predictor is capable of predicting branch direction and target addresses, augmented with multiple auxiliary direction, target, and power predictors. Predictions are made asynchronously, and later integrated into the processor pipeline. The design is optimized for the unique workloads executed on these enterprise-class systems, including compute intensive and both large instruction and data footprint workloads. This paper highlights the major operations and functions of the IBM z15 branch predictor, including its pipeline, prediction structures and verification methodology. Explanations as to how the design matured to its current state are also provided.