ОЦЕНКА ЭФФЕКТИВНОСТИ РЕШЕНИЙ НА ОТДЕЛЬНЫХ УРОВНЯХ В СИСТЕМЫ BIM

The paper presents the results of research in the field of the use of innovative technologies in the design of buildings. The modern technologies of information modeling, in particular, BIM, which makes it possible to represent the building not only in three-dimensional space, but also allows designing it in the dynamic system « design - construction – operation » are considered. The experience of using BIM technologies is based on identifying errors at the initial design stage and the possibility of their elimination at the same stage. The development of mechanisms for detecting design errors and defects formed the basis of the task set in the work. A model for signaling about the detection of defects has been developed, and the problem of stochastic modeling of the qualitative parameters of the designed object has been solved.

It is well known that noise and detection error can affect the performances of an adaptive optics (AO) system. Effects of noise and detection error on the phase compensation effectiveness in a dynamic AO system are investigated by means of a pure numerical simulation in this paper. A theoretical model for numerically simulating effects of noise and detection error in a static AO system and a corresponding computer program were presented in a previous article. A numerical simulation of effects of noise and detection error is combined with our previous numeral simulation of a dynamic AO system in this paper and a corresponding computer program has been compiled. Effects of detection error, readout noise and photon noise are included and investigated by a numerical simulation for finding the preferred working conditions and the best performances in a practical dynamic AO system. An approximate model is presented as well. Under many practical conditions such approximate model is a good alternative to the more accurate one. A simple algorithm which can be used for reducing the effect of noise is presented as well. When signal to noise ratio is very low, such method can be used to improve the performances of a dynamic AO system.

Software engineers often need to identify and correct design defects, i.e., recurring design problems that hinder development and maintenance by making programs harder to comprehend and/or evolve. While detection of design defects is an actively researched area, their correction — mainly a manual and time-consuming activity — is yet to be extensively investigated for automation. In this paper, we propose an automated approach for suggesting defect-correcting refactorings using relational concept analysis (rca). The added value of rca consists in exploiting the links between formal objects which abound in a software re-engineering context. We validated our approach on instances of the Blob design defect taken from four different open-source programs.KeywordsDesign DefectsRefactoringRelational Concept Analysis

Design defects come from poor design choices and have the effect of degrading the quality of object-oriented designs.Therefore, they present opportunities for improvements.However, design defects have not been precisely specified and there are few appropriate tools that allow their detection as well as their correction. Our goal is to provide a systematic method to specify systematically design defects precisely and to generate automatically detection and correction algorithms from their specifications. The detection algorithms are based not only on metrics but also on semantical and structural properties whereas the correction algorithms are based on refactorings. We apply and validate these algorithms on open-source object-oriented programs to show that our method allows a systematic specification, a precise detection, and a suitable correction of design defects.

Reliability and real-time responsiveness in safety-critical systems have traditionally been achieved using error detection mechanisms, such as LockStep, which require pre-configured checker cores, strict synchronisation, static error detection regions, or limited preemptions. However, these core-bound hardware mechanisms often lead to significant resource over-provisioning and diminished real-time performance in modern systems where tasks with varying reliability requirements are consolidated on shared processors for efficiency and cost reduction. To address these challenges, this work presents FlexStep, a systematic solution that integrates hardware and software across the SoC, ISA, and OS scheduling layers. FlexStep features a novel microarchitecture that supports dynamic core configuration and asynchronous, preemptive error detection. The FlexStep architecture naturally allows for flexible task scheduling and error detection, enabling new scheduling algorithms that enhance both resource efficiency and real-time schedulability.

Early detection and treatment of refractive defects during school age are essential to avoid irreversible future vision loss and potential school problems. Previously, vision screening of preschool children used methods based on subjective visual acuity; however, technologies such as photorefraction have promoted the detection of refractive errors quickly and easily. In this study, 1347 children from 10 schools in Madrid aged 4 to 12 years participated in a program of early detection of visual problems, which consisted of visual screening composed of anamnesis and photorefraction with a PlusOptix A12R. The prevalence of refractive errors was analyzed in terms of spherical equivalent, cylinder and its orientation, and potential cases of development of high myopia or amblyopia. Hyperopia predominates in the early years, but the number of myopic subjects is higher than that of hyperopic subjects from the age of ten onwards. At all ages, the predominant orientation of astigmatism was with-the-rule. On average, 80% of the myopic subjects were uncorrected. Potential high myopia increased with age, from 4 to 21% of the measured population. Potential amblyopia cases decreased across age groups, from 19 to 13.7%. There is a need to raise awareness of the importance of vision screening at school age to address vision problems.

Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection technique, called fingerprinting , that detects differences in execution across a dual modular redundant (DMR) processor pair. Fingerprinting summarizes a processor's execution history in a hash-based signature; differences between two mirrored processors are exposed by comparing their fingerprints. Fingerprinting tightly bounds detection latency and greatly reduces the interprocessor communication bandwidth required for checking. This paper presents a study that evaluates fingerprinting against a range of current approaches to error detection. The result of this study shows that fingerprinting is the only error detection mechanism that simultaneously allows high-error coverage, low error detection bandwidth, and high I/O performance.

Polynomial multiplication stands out as a highly demanding arithmetic process in the development of post-quantum cryptosystems. The importance of the number-theoretic transform (NTT) extends beyond post-quantum cryptosystems, proving valuable in enhancing existing security protocols such as digital signature schemes and hash functions. CRYSTALS-KYBER stands out as the sole public key encryption (PKE) algorithm chosen by the National Institute of Standards and Technology (NIST) in its third round selection, making it highly regarded as a leading post-quantum cryptography (PQC) solution. Faults have the potential to disrupt cryptographic systems, compromise data integrity, and enable side-channel attacks, making the incorporation of robust error detection mechanisms essential. This article introduces algorithm-level fault detection schemes in the NTT multiplication using Negative Wrapped Convolution ( NWC ) and the NTT tailored for Kyber Round 3, representing a significant enhancement compared with previous research. We evaluate this through the simulation of a fault model, ensuring that the conducted assessments accurately mirror the obtained results. Our fault detection scheme is designed to address both malicious fault injection attacks on Kyber and naturally occurring faults. Furthermore, we assessed the effectiveness of the proposed error detection scheme for the NTT implemented in both NWC and Kyber , using AMD/Xilinx Artix-7 FPGA, HLS and processor-based approaches. In our FPGA implementation of NWC , the integration of our error detection approach achieves near-100% fault coverage with minimal area overhead and results in only a 12% increase in latency compared with the original hardware design. Finally, we attained an error detection ratio of nearly 100% for the NTT operation in Kyber , with a clock cycle overhead of 16% on the Cortex-A72 processor.

For facilitating error localization, software-based error detection techniques have been proposed and EDM (error detection mechanisms) transformation is one of these techniques. To discuss the effectiveness of EDM for electrical bug localization, two scenarios are considered; (1) localizing an electrical bug occurred in the original program, and (2) localizing as many potential bugs as possible. We experimentally evaluated the error detection performance in these two scenarios under dynamic power supply noise. Experimental results show that the EDM transformation customized for quick error detection cannot locate electrical bugs in the original program in the firs scenario, but it is useful for findin potential bugs in the second scenario.

Highly water-soluble AIEgen for α-amylase activity ultrasensitive detection and ovarian cancer rapid theranostic.

Design defects are one of the main reasons for the decline of software design quality. Effective detection of design defects plays an important role in improving software maintainability and scalability. On the basis of defining software design defects, according to C&K design metrics and heuristics, this paper extracts the relevant features of design defects. Based on classical machine learning methods, classifiers are trained for design defect, and candidate designs are classified by classifiers, so as to identify whether there is a design defect in the design. Experiments show that the method has high accuracy and recall rate in identifying design defects.

Lightweight block ciphers are proposed for Internet of Things (IoT) edge devices to ensure secure data transmission with limited resources. However, past research has been designed on ideal channel models, disregarding the possibility of ciphertext errors caused by channel interference during actual transmission. This omission poses difficulties in ensuring the reliability of the ciphertext, especially in the Internet of Medical Things (IoMT) where resources are limited and data accuracy requirements are high. Designing a highly secure and reliable lightweight block cipher for such situations is one of the most challenging tasks. Hence, we propose a lightweight block cipher ECLBC with error detection and correction mechanisms. For security, ECLBC not only achieves a certain security level in fewer rounds but also achieves a mode transition within AND-Rotation-XOR (AND-RX) lightweight block ciphers. This transition involves a shift from the Feistel to the Substitution-Permutation Network (SPN) and from half-round key XOR to full-round key XOR. For reliability, ECLBC supports detecting and correcting erroneous ciphertext due to channel interference. Given the resource-constrained nature of IoMT devices, we implement the detection and correction mechanism of ECLBC based on the linear block code. Finally, various classical cryptography methods are employed to analyze the performance and security of the ECLBC.

<div class="htmlview paragraph">Thermal testing of spacecraft electronic units prior to flight provides effective detection of design, process and workmanship defects. Thermal testing subjects units to cold and hot thermal environments beyond those expected in flight. The strength of screening effectiveness depends upon the number of cycles, the temperature range, and the temperature transition rate. MIL-HDBK-344 provides insight into the incurred stresses and quantitative value (precipitation efficiency) of the screening environment using these three test parameters.</div> <div class="htmlview paragraph">In this paper, MIL-HDBK-344 topics applicable to thermal testing of space hardware are summarized and comparisons are made between test environment strengths computed from MIL-HDBK-344 and MIL-STD-1540E. The weighting of these aforementioned test parameters in the precipitation efficiency equation are discussed and assessed. It was found that the fatigue equivalency equations in MIL-STD-1540E specify a significantly larger number of required cycles for various test temperature ranges as compared to cycles computed from MIL-HDBK-344 equations.</div>

The ubiquity of complex devices built on systems on chip (SoC) with multiple processor cores poses new challenges for developers of embedded systems. New development tools specifically designed for complex systems on chip can help solve them, but these tools are usually limited by the functionality of debugging support tools. High-quality debugging support with advanced features is necessary to take full advantage of complex SoC devices while reducing development time. The article discusses various mechanisms and ways to implement support for debugging systems on chip designed for complex real-time systems used, for example, in the Internet of Things (IoT) paradigm. This review includes an assessment of the available solutions and their suitability for use with the next generation of complex systems on chip with multiple processor cores. It is shown that many existing solutions do not allow developers to easily take advantage of complex functions integrated into the next-generation SoC. The basic debugging support functions for multicore SoCs are summarized and discussed. Recommendations are given for SoC develo­pers and for the future direction of research in this area in order to provide a more suitable basis for new development tools. Such tools are extremely necessary for all embedded hard real-time systems and are of high importance for minimizing the complexity of their development. Modern systems and devices implementing the Internet of Things paradigm are increasingly required to have sufficiently high real-time performance while maintaining low power consumption. These requirements lead to the cre­ation of multicore SoC solutions with support for a wide range of peripheral devices and communication protocols. The systems are limited by the requirements for working in harsh conditions, such as, for example, in the engine compart­ment of a car or on a radar tower. The development of embedded hard real-time systems, in which a task that fails to be completed on time can lead to physical damage of the device, is a complex process. Effective tools, such as interactive debuggers and profilers, are an integral part of solving these problems and are vital for developing reliable embedded systems. Modern technologies now allow the integration of the entire system on a single silicon chip, known as a system on a chip (SoC), which leads to the relocation of existing external interfaces, widely used for development purposes, to the chip. Traditionally, communication within an embedded system is carried out using an external processor system bus, which is implemented in the form of tracks on a printed circuit board. The printed circuit board must support the appropriate interfaces of development tools that require a physical connection, such as, for example, logic analyzers and oscilloscopes. Previously, placing exter­nal interfaces on a chip left fewer options for external analysis tools and, in fact, makes developers "blind" to the internal state of the SoC. Without a reliable and consistent representation of the state of the embedded system, the detection of defects or errors in the system may become difficult or even impossible. The main solution to the problem of the lack of external interfaces is to provide access to internal nodes from outside the system through existing interfaces. There are many different approaches to achieving the required visibility, and they are outlined in this review.

With technology scaling and complexity, better error detection and correction mechanisms within chips and systems are becoming increasingly important in order to provide sufficient protection against both soft and hard errors. Verifying the correctness of error detection circuits and ensuring they provide enough design coverage is a hard problem which usually involves substantial amount of manual work. This problem is even more challenging in the presence of different design methodologies, such as with the inclusion of third party IP blocks where functional descriptions of logic designs may not be available. This paper addresses the problem by proposing a completely automated RTL-based verification flow for error detection and correction circuits. Several related challenges are solved: first, that of identification of potential error detection circuits in logic designs where no functional description or methodology hints are given. Second, identification of structures of the latches that are potentially protected by such error detection circuits. Third, using formal verification for ensuring that the implemented circuits for resiliency indeed detect all single bit errors in the latches they are intended to cover. The approach is described with parity detection as an example, although it is extensible to other coding methods such as ECC and state orthogonality checking. Novel algorithms are given and results on industrial designs are presented.