용융 금속 TSV 충전을 위한 저열팽창계수 SiC 복합 충전 솔더의 개발

Recently, the downsizing and high-performing semiconductor packages have been developed and 3D packaging has been spurred research into reliability of TSV (through silicon via) [l]-[9]. In conventional SiP (System in Package), several semiconductor chips had been arranged in a plate. It is difficult to correspond to downsizing and high-performing of electronic devices because that large area is occupied by the package. The semiconductor chips have been stacked and TSVs have been used to communicate between the chips in order to solve above problems. The 3D stacked structure which was developed by ASET (Association of Su per-Advanced Electronics Technologies) [10] is shown in Fig.1. TSV (copper) is electrode which passes through silicon chip and micro bump (copper) [11] is arranged between chips. Heat is generated in package due to operation of semiconductor device, and it has been reported that silicon is broken by thermal stress which is depend on temperature increment. In case of 3D-SIP, higher stress has to be considered in the most outer part of TSV and micro bump structure due to warp and mismatch of CTE (coefficient of thermal expansion) of material. Therefore simulations with detail model must be desired for more accurate evaluation of stresses in Si chips and TSVs. However it is difficult that all of TSVs and micro bumps in chips were modeled due to large number of numerical data even if the latest computing systems have been adopted.

Thermal conduction and mechanical stresses in through silicon via (TSV) structures in three dimensional system in package (3D SiP) under device operation condition were discussed. A large scale simulator, ADVENTURECluster® based on finite element method (FEM) was used to simulate the effects of voids formed inside Cu TSVs on the thermal conduction and mechanical stresses in the TSV structure. The thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses in the TSV structure in 3D SiP were carried out under thermal condition due to power ON/OFF of device. In case that void was not present inside the TSV, the stresses in TSV were close to the hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. Maximum principal stress of the Si chip in the TSV structure for the case without voids was lower than that of the bending strength of silicon. However, the level of the stresses in the Si chips should not be negligible for damages to Si chips. In case that void was present inside the TSV, stress concentration was occurred around the void in the TSV. The magnitude of the equivalent stress in the TSV was lower than the yield stress of copper. The magnitude of the maximum principal stress of the Si chip was lower than that of the bending strength of silicon. However, its level should not be negligible for damages to TSVs and Si chips. The stress on inner surfaces of Si chip was slightly reduced due to the presence of a void in the TSV.

Thermal conduction and mechanical strength around TSV (Through Silicon Via) structures of 3D SiP (Three Dimensional System in Package) were discussed both cases of with and without void in TSV by using a large scale simulator based on FEM, ADVENTURECluster® for ensuring the reliability of 3D SiP. In the results, the thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses around TSV structure in 3D SiP under thermal cycle condition due to power ON/OFF were carried out. In case that void was not in TSV, stresses in TSV were close to hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. However, the level of the stresses, especially in Si chips, should not be negligible in inducing damages to TSVs and Si single crystals. In case that void was in TSV, stress was concentrated around void in TSV and the magnitude of the equivalent stress was lower than the yield stress of copper. The level of stresses applied to Si chip was slightly reduced due to void in TSV. However, its level should not be negligible in inducing damages to TSVs and Si single crystals.

Cu-filled through-silicon vias (TSVs) are an essential building block of 3D and 2.5D integrated chips. In the TSV-mid processing flow, which has emerged as an industry mainstream, one or more on-chip wiring levels are formed after the TSV Cu fill is completed, which exposes the fill to peak temperatures of up to 400 °C. Due to the higher coefficient of thermal expansion (CTE) of Cu than the surrounding silicon and dielectrics, the TSV fill protrudes above the level previously defined by the TSV chemical mechanical polishing (CMP) step. Even after returning to room temperature, the top of the TSV will not occupy the same space due to plastic deformation during the thermal treatment. This phenomenon is known as Cu protrusions, pumping, or popping. Excessive amounts of Cu protrusion present a risk to yields and reliability because the expansion can damage dielectrics and wiring above or adjacent to the TSVs. In this study, we report the underlying mechanisms as well as process remedies for Cu protrusions. The SEMATECH 5 um × 50 um TSV process and learning vehicle is used to conduct process split experiments comparing various plating chemistries, plating recipes, and post-plating anneal conditions. Stresses in the surrounding silicon are studied by micro-Raman, and a distinct signature distinguishing good from bad Cu protrusion behavior is identified. Cu material properties such as contamination, grain size, grain orientation, and strain may also influence the protrusion behavior; these factors are studied by micro-secondary ion mass spectroscopy (SIMS) and electron backscatter spectroscopy (EBSD). Our results shows that the choice of plating chemistry and subsequent optimized post-plating anneal are the main factors in suppressing Cu protrusions. Our best known method is able to reduce Cu protrusions to about 15 nm after typical thermal loads.

Flip chip ball grid array (FCBGA) is one of the most broadly used package types in different types of electronic packages. In a FCBGA package, the die/ silicon is flipped and attached to substrate with help of copper pillars. The material property coefficient of thermal expansion (CTE) mismatch between die/ silicon and substrate materials like core, dielectric material results in package thermal warpage and may lead to thermo-mechanical related failures in electronic packages. CTE can be defined as the rate at which a material expands with change in the temperature. Material expansion increases with a higher CTE. The CTE of die/ silicon is lower than the overall CTE of organic substrate. During reflow, as an electronic package cools down it warps in a convex or crying shape which indicates positive package warpage, and as the electronic package heats up it warps in a concave or smiling shape which indicates negative package warpage. Induced thermal warpage during the electronic package reflow assembly process is an important factor affecting the package assembly and thermo-mechanical reliability of FCBGA packages; therefore, precise package thermal warpage prediction is one of the most significant parameters for the electronic package design processes. In this study, the effect of different electronic package parameters (core material CTE, core thickness, package type) of the FCBGA package on its warpage are assessed by using finite element analysis (FEA) mechanical simulation methodology. A bare die FCBGA package having substrate core material with lower coefficient of thermal expansion (CTE) shows lower package warpage as the mismatch between die/ silicon and substrate core material CTE becomes dominant factor to drive the package warpage. To understand the package warpage trend, warpage is evaluated at room temperature & high/ reflow temperature. The package warpage trend is reversed for larger FCBGA packages with stiffener ring. Substrate core material with higher CTE shows lower package warpage as CTE mismatch between substrate core material and stiffener ring material (steel/copper) CTE becomes the dominant factor to drive the package warpage. The counter intuitive package warpage data from mechanical simulation is compared with shadow-moire test data and it shows good correlation and validates the simulations findings. Based on this work, it is recommended that a thorough investigation for large size packages be conducted before choosing packaging materials. This work shall provide new insights for package designers to optimize thermal warpage and stress during package initial design phase.

3D IC integration is the latest technological breakthrough for maximizing its performance while reducing wiring lengths, interconnection latency, and power consumption. Through-silicon via (TSV) is an essential feature of the 3D IC integration. Filling high aspect ratio TSVs by the conductive materials can be a challenging task. Copper electrodepostion is often adopted due to its optimal electrical preoperties, simplicity, and cost-effectiveness. However, the coefficient of thermal expansion (CTE) of copper is much higher (16.7 ppm/℃) than that of silicon (2.3 ppm/℃). Therefore, the CTE mismatch between copper and silicon substrate can induce thermal stresses, which may lead to TSV protrusion and interfacial delamination. In previous studies, this is mostly managed via suitable heat treatment. This study however proposes a novel method for controlling TSV protrusion. Copper with JGB (Janus Green B, C30H31ClN6) concentration increases (and at the level of 0.2mM of JGB), while the sheet resistance decrease by 7% for the initial resistance. Here, the crystal growth is not observed that is due to impurity pinning or solute dragging effect at grain boundaries. This leads to the conclusion that controlling impurity contents may relieve stress of TSV overhang area. To prevent TSV protrusion, we also perform the same concentration split tests on TSV pattern wafers. Figure 1. EBSD IPF maps of Cu electrodeposit after annealing at 80 ℃ for 90 min with various JGB concentrations of (a) 0, (b) 0.01, (c) 0.03, (d) 0.1, (e) 0.2 and (f) 1 mM in the Cu plating bath. Figure 1

Through Silicon Via (TSV) technology has been a preferred and promising strategy to achieve the reliable interconnection for the integration of 3D IC. The temperature made some changes within the procedures of the manufacture of TSV and the adoption of chips because of the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials adopted within TSV structure, important thermal stress is going to be induced under the thermal load. The stresses are possible to cause different reliability problems. Dimension parameters are going to influence TSV’s thermal behaviors. For the purpose of optimizing the design of TSV, Cu-filled TSV’s numerical model had been set up for simulating and analyzing the influence of the thickness of SiO 2 , aspect ratio (AR), diameter and shape upon TSV thermal stress within the paper. The outcomes of the simulation present that the maximum of the areas of equivalent stress always happens at the bottom and top of the interface of Cu/SiO 2 . The aspect ratio’s influence on the equivalent stress is rather small when aspect ratio is more than 6 for vertical TSV. Vertical TSV with thicker SiO 2 layer may improve its reliability. However, the SiO 2 layer thickness does not have obvious influence for the inclined TSV upon equivalent stress.

New electronic devices with small size and low power consumption are in demand in recent years. Miniaturization and complex product are required in modern electronics for more functionality in the smaller electronic package. To overcome such issues, 3D packages or package on package (PoP) are introduced. The 3D packaging is stacking of chip on top of another which is emerging as a powerful technology that satisfies such integrated circuit (IC) package demands. A 3D package using through silicon vias (TSVs) has emerged as an effective technology for future interconnection requirements. The mismatch of coefficient of thermal expansion (CTE) of the SiO2 and copper used in TSV can induce a lot of thermal stresses. The stress developed at interfaces results in the interfacial delamination of TSV, which is mainly driven by a shear stress concentration at the point. The developed thermal stresses are critical for the thermo-mechanical reliability of the 3D package. In this paper, the effect of package structure on the failure metric of the 3D package has been studied. J-integral has been used to quantify the crack driving force. The crack is modeled at the TSV and BEOL (Back End of the Line) and the die-substrate thickness is varied and studied during chip attachment process and under thermal cycling load for optimizing the die and substrate thickness design [1]. Finite Element method have been used to analyze the thermo-mechanical stresses and fracture parameters in TSV structures 3D package. For this study, full field compact modeling methodology [2] has been leveraged for the ease of FEA using ANSYS Workbench 17.2. An optimized package assembly was obtained to reduce the crack driving energy at the TSV region and in the BEOL dielectric layer. A design approach has been proposed to mitigate brittle failure issues thus improving the thermo-mechanical reliability of the 3D package.

Metal Matrix Composite Thermal Management Materials

Through silicon via (TSV) technology has attracted much attention as a key method to realize chip stacking and interposers interconnected of 3D packaging. Due to the thermal load during fabrication and operation of TSV structure, the thermal stress will be produced owing to the structural material high CTE mismatch, which may lead to the failure of the TSV structure. In the case of uneven thermal load, the SiO 2 with low thermal conductivity has a blocking effect on heat flow, thus it has a non-ignorable effect on thermal stress. In this paper, a planar TSV model of coupled thermal stress fields is established to demonstrate the influence of directional heat transfer. The influence of the thickness and structural parameters of SiO 2 insulation layer on thermal stress is studied by finite element modeling. The simulation results show that larger SiO 2 insulation thickness and smaller structural parameters q (q=D/P) can reduce the threat of thermal stress within the acceptable range. In addition, BCB and Parylene layer that replacing the SiO 2 insulating layer can significantly reduce the thermal stress of the TSV structure. The average reduction is from 30% to 45% in majority region, and the reduction even reaches 70% at the Cu/SiO 2 interface.

Grain characteristics of copper filler have an important influence on physical properties of through silicon vias (TSVs) in three-dimensional (3D) packaging. Due to the mismatch of coefficients of thermal expansion (CTE) between the copper and silicon, there exist obvious thermal stresses when the TSV structure is bearing thermal load. However, the elastic response characteristics of copper can be affected distinctly by the size, shape and orientation of copper grains in TSVs. These effects can not be ignored, especially for 3D ICs undergoing continuous miniaturization and increasing integration. In this study, the grain growth and evolution of a typical copper filler in the TSV structure is dynamically simulated and investigated by using Monte Carlo method (MCM), then the thermo-mechanical behavior of TSVs with considering the grain characteristics of copper filler is studied with combined MCM and finite element method (FEM), i.e., MC-FE method. Besides, the effects of grain evolution on the protrusion of copper filler in the TSV is also investigated. Simulation results are presented for providing more quantitative description and comprehensive understanding of the influences of microstructure evolution of copper filler on the thermo-mechanical behavior of Cu-filled TSVs.

In the late 1990s, the technology that is stacked multiple silicon chips on the package was developed [1]. Then SiP (System in Package) constructed with CPU and memory into a package is appeared. Recently, downsizing and high-performing of semiconductor packages have been studied. In conventional SiP, several semiconductor chips had been arranged in a plate [2-6]. Therefore, it is difficult to correspond to downsizing and high-performing of electronic devices because that large area was occupied by the package. In order to solve above problems, semiconductor chips have been stacked and TSV (Through Silicon Via) have been used to communicate between the mutual chips. The 3D-stacked structure for ultra high speed camera developed by ASET (Association of Super-Advanced Electronics Technologies)[7, 8] is shown in Fig.1. TSV (copper) is electrode through silicon chip and micro bump (copper)[9] is arranged between chips. Heat is generated in package due to operation of semiconductor device, and it has been reported that silicon is broken by thermal stress depend on temperature increment. In case of 3D-SiP, higher stress has to be considered in the most outer part of TSV and micro bump structure due to warp by difference of expansion of material. Therefore simulations with detail model must be desired for accurate evaluation of stresses in Si chips and TSVs. However it is difficult that all of TSVs and micro bumps in package were modeled due to large number of numerical data even if the latest computing systems have been adopted. In this study, stresses of Si and TSV in 3D SiP were discussed with the model which was partially replaced by simplified semiconductor chip. It was shown that inner part of package was replaced on simplified model and outer part is the model constructed by Si chip, TSVs and micro bumps.

Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of the major challenges of 3D integration. In this paper, different materials for the cores of the vias and the interposers are investigated to find the best possible combination that can reduce crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored glass and silicon as interposer materials. The simulation results indicate that glass is the best option as interposer material although silicon interposer has some distinct advantages. For via cores three materials — copper (Cu), tungsten (W) and Cu-W bimetal are considered. From the analysis it can concluded that W would be better for high frequency applications due to lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be in between Cu and W. However, W has a thermal expansion coefficient close to silicon. Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission coefficient and crosstalk in the vias.

The technique of the through silicon via (TSV) filling with copper plays an important role in the 3D packaging to miniaturize connection distance, decrease energy consumption and improve integration density. The nano-scale TSV of the vertical interconnection is obligatory to be developed to reach sub-micron interconnect pitches. However, the reliability of the nano-TSV is a serious concern because thermo-mechanical stresses are varied in the TSV under thermal loadings due to the mismatch of the coefficients of thermal expansion (CTE) between the copper and the surrounding silicon. The high stresses may cause crack propagation and even failures. In this study, the finite element analyses (FEA) for the nano-TSV array with different sizes and patterns were performed. The submodeling method was used in the analysis for a 3D packaged device to reveal the influence of the critical parameters, i.e., the aspect ratio of TSV, the ratio of pitch to diameter and the TSV array layouts. The trilateral and quadrilateral layouts of nano-TSV array were considered in the analysis. Thus, appropriate design suggestions for the nano-TSV array were proposed. The study results assist to optimize the nano-TSV geometry and improve the reliability of the 3D package with nano-TSV.

Solder joints in electronic packages are frequently exposed to thermal cycling in both real-life applications and accelerated thermal cycling tests. Cyclic temperature leads the solder joints to be subjected to cyclic mechanical loading and often accelerates the cracking failure of the solder joints. The cause of stress generated in thermal cycling is usually attributed to the coefficients of thermal expansion (CTE) mismatch of the assembly materials. In a die-attach structure consisting of multiple layers of materials, the effect of their CTE mismatch on the thermal stress at a critical location can be very complex. In this study, we investigated the influence of different materials in a die-attach structure on the stress at the chip–solder interface with the finite element method. The die-attach structure included a SiC chip, a SAC solder layer and a DBC substrate. Three models covering different modeling scopes (i.e., model I, chip–solder layer; model II, chip–solder layer and copper layer; and model III, chip–solder layer and DBC substrate) were developed. The 25–150 °C cyclic temperature loading was applied to the die-attach structure, and the change of stress at the chip–solder interface was calculated. The results of model I showed that the chip–solder CTE mismatch, as the only stress source, led to a periodic and monotonic stress change in the temperature cycling. Compared to the stress curve of model I, an extra stress recovery peak appeared in both model II and model III during the ramp-up of temperature. It was demonstrated that the CTE mismatch between the solder and copper layer (or DBC substrate) not only affected the maximum stress at the chip–solder interface, but also caused the stress recovery peak. Thus, the combined effect of assembly materials in the die-attach structure should be considered when exploring the joint thermal stresses.