Thermal stresses around TSV structure in stacked Si chips

In the late 1990s, the technology that is stacked multiple silicon chips on the package was developed [1]. Then SiP (System in Package) constructed with CPU and memory into a package is appeared. Recently, downsizing and high-performing of semiconductor packages have been studied. In conventional SiP, several semiconductor chips had been arranged in a plate [2-6]. Therefore, it is difficult to correspond to downsizing and high-performing of electronic devices because that large area was occupied by the package. In order to solve above problems, semiconductor chips have been stacked and TSV (Through Silicon Via) have been used to communicate between the mutual chips. The 3D-stacked structure for ultra high speed camera developed by ASET (Association of Super-Advanced Electronics Technologies)[7, 8] is shown in Fig.1. TSV (copper) is electrode through silicon chip and micro bump (copper)[9] is arranged between chips. Heat is generated in package due to operation of semiconductor device, and it has been reported that silicon is broken by thermal stress depend on temperature increment. In case of 3D-SiP, higher stress has to be considered in the most outer part of TSV and micro bump structure due to warp by difference of expansion of material. Therefore simulations with detail model must be desired for accurate evaluation of stresses in Si chips and TSVs. However it is difficult that all of TSVs and micro bumps in package were modeled due to large number of numerical data even if the latest computing systems have been adopted. In this study, stresses of Si and TSV in 3D SiP were discussed with the model which was partially replaced by simplified semiconductor chip. It was shown that inner part of package was replaced on simplified model and outer part is the model constructed by Si chip, TSVs and micro bumps.

Thermal conduction and mechanical stresses in through silicon via (TSV) structures in three dimensional system in package (3D SiP) under device operation condition were discussed. A large scale simulator, ADVENTURECluster® based on finite element method (FEM) was used to simulate the effects of voids formed inside Cu TSVs on the thermal conduction and mechanical stresses in the TSV structure. The thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses in the TSV structure in 3D SiP were carried out under thermal condition due to power ON/OFF of device. In case that void was not present inside the TSV, the stresses in TSV were close to the hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. Maximum principal stress of the Si chip in the TSV structure for the case without voids was lower than that of the bending strength of silicon. However, the level of the stresses in the Si chips should not be negligible for damages to Si chips. In case that void was present inside the TSV, stress concentration was occurred around the void in the TSV. The magnitude of the equivalent stress in the TSV was lower than the yield stress of copper. The magnitude of the maximum principal stress of the Si chip was lower than that of the bending strength of silicon. However, its level should not be negligible for damages to TSVs and Si chips. The stress on inner surfaces of Si chip was slightly reduced due to the presence of a void in the TSV.

Thermal conduction and mechanical strength around TSV (Through Silicon Via) structures of 3D SiP (Three Dimensional System in Package) were discussed both cases of with and without void in TSV by using a large scale simulator based on FEM, ADVENTURECluster® for ensuring the reliability of 3D SiP. In the results, the thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses around TSV structure in 3D SiP under thermal cycle condition due to power ON/OFF were carried out. In case that void was not in TSV, stresses in TSV were close to hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. However, the level of the stresses, especially in Si chips, should not be negligible in inducing damages to TSVs and Si single crystals. In case that void was in TSV, stress was concentrated around void in TSV and the magnitude of the equivalent stress was lower than the yield stress of copper. The level of stresses applied to Si chip was slightly reduced due to void in TSV. However, its level should not be negligible in inducing damages to TSVs and Si single crystals.

Among through silicon via (TSV) technologies, for replacing Cu filling method, the method of molten solder filling has been proposed to reduce filling cost and filling time. However, because Sn alloy which has a high coefficient of thermal expansion (CTE) than Cu, CTE mismatch between Si and molten solder induced higher thermal stress than Cu filling method. This thermal stress can deteriorate reliability of TSV by forming defects like void, crack and so on. Therefore, we fabricated SiC composite filling material which had a low CTE for reducing thermal stress in TSV. To add SiC nano particles to molten solder, ball-typed SiC clusters, which were formed with Sn powders and SiC nano particles by ball mill process, put into molten Sn and then, nano particle-dispersed SiC composite filling material was produced. In the case of 1 wt.% of SiC particle, the CTE showed a lowest value which was a <TEX>$14.8ppm/^{\circ}C$</TEX> and this value was lower than CTE of Cu. Up to 1 wt.% of SiC particle, Young's modulus increased as wt.% of SiC particle increased. And also, we observed cross-sectioned TSV which was filled with 1 wt.% of SiC particle and we confirmed a possibility of SiC composite material as a TSV filling material.

Grain characteristics of copper filler have an important influence on physical properties of through silicon vias (TSVs) in three-dimensional (3D) packaging. Due to the mismatch of coefficients of thermal expansion (CTE) between the copper and silicon, there exist obvious thermal stresses when the TSV structure is bearing thermal load. However, the elastic response characteristics of copper can be affected distinctly by the size, shape and orientation of copper grains in TSVs. These effects can not be ignored, especially for 3D ICs undergoing continuous miniaturization and increasing integration. In this study, the grain growth and evolution of a typical copper filler in the TSV structure is dynamically simulated and investigated by using Monte Carlo method (MCM), then the thermo-mechanical behavior of TSVs with considering the grain characteristics of copper filler is studied with combined MCM and finite element method (FEM), i.e., MC-FE method. Besides, the effects of grain evolution on the protrusion of copper filler in the TSV is also investigated. Simulation results are presented for providing more quantitative description and comprehensive understanding of the influences of microstructure evolution of copper filler on the thermo-mechanical behavior of Cu-filled TSVs.

Through Silicon Via (TSV) technology has been a preferred and promising strategy to achieve the reliable interconnection for the integration of 3D IC. The temperature made some changes within the procedures of the manufacture of TSV and the adoption of chips because of the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials adopted within TSV structure, important thermal stress is going to be induced under the thermal load. The stresses are possible to cause different reliability problems. Dimension parameters are going to influence TSV’s thermal behaviors. For the purpose of optimizing the design of TSV, Cu-filled TSV’s numerical model had been set up for simulating and analyzing the influence of the thickness of SiO 2 , aspect ratio (AR), diameter and shape upon TSV thermal stress within the paper. The outcomes of the simulation present that the maximum of the areas of equivalent stress always happens at the bottom and top of the interface of Cu/SiO 2 . The aspect ratio’s influence on the equivalent stress is rather small when aspect ratio is more than 6 for vertical TSV. Vertical TSV with thicker SiO 2 layer may improve its reliability. However, the SiO 2 layer thickness does not have obvious influence for the inclined TSV upon equivalent stress.

Three-dimensional (3D) integration of silicon microelectronic devices improves the electronic functions of devices and minimizes packaging density drastically. A through-silicon via (TSV) structure is indispensable for maximizing the density of interconnections among the stacked silicon chips. However, since the TSV structure is surrounded by silicon, and there is large mismatch in materials properties between metallic materials used for the TSV structure and silicon, thermal stress is essentially generated around the TSV structure during their fabrication process and operating conditions. Recently, electroplated copper thin films have started to be applied to the interconnection material in the TSV structure because of its low electric resistivity and high thermal conductivity. However, the electrical resistivity of the electroplated copper thin films surrounded by SiO2 was found to vary drastically comparing with those of the conventional bulk material. This was because that the electroplated copper thin films consisted of grains with low crystallinity and grain boundaries, in other words, abnormally high defect density. Thus, both the crystallinity and electrical properties of the TSV structure was investigated quantitatively by changing their electroplating conditions and thermal history after the electroplating. It was observed that many voids and hillocks appeared in the TSV structures depending on the electroplating conditions. It was also found that the stress-induced migration occurred after the high temperature annealing which was introduced for improving the crystallinity of the electroplated films. Therefore, it is very important to evaluate the crystallographic quality of the electroplated copper thin films after electroplating to assure both the mechanical and electrical properties of the films.

New electronic devices with small size and low power consumption are in demand in recent years. Miniaturization and complex product are required in modern electronics for more functionality in the smaller electronic package. To overcome such issues, 3D packages or package on package (PoP) are introduced. The 3D packaging is stacking of chip on top of another which is emerging as a powerful technology that satisfies such integrated circuit (IC) package demands. A 3D package using through silicon vias (TSVs) has emerged as an effective technology for future interconnection requirements. The mismatch of coefficient of thermal expansion (CTE) of the SiO2 and copper used in TSV can induce a lot of thermal stresses. The stress developed at interfaces results in the interfacial delamination of TSV, which is mainly driven by a shear stress concentration at the point. The developed thermal stresses are critical for the thermo-mechanical reliability of the 3D package. In this paper, the effect of package structure on the failure metric of the 3D package has been studied. J-integral has been used to quantify the crack driving force. The crack is modeled at the TSV and BEOL (Back End of the Line) and the die-substrate thickness is varied and studied during chip attachment process and under thermal cycling load for optimizing the die and substrate thickness design [1]. Finite Element method have been used to analyze the thermo-mechanical stresses and fracture parameters in TSV structures 3D package. For this study, full field compact modeling methodology [2] has been leveraged for the ease of FEA using ANSYS Workbench 17.2. An optimized package assembly was obtained to reduce the crack driving energy at the TSV region and in the BEOL dielectric layer. A design approach has been proposed to mitigate brittle failure issues thus improving the thermo-mechanical reliability of the 3D package.

Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, 3-D integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermomechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effects of thermally induced stresses on the interfacial reliability of TSV structures. First, 3-D distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semianalytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results from finite element analysis (FEA). The stress analysis suggests interfacial delamination as a potential failure mechanism for the TSV structure. An analytical solution is then obtained for the steady-state energy release rate as the upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. With these results, the effects of the TSV dimensions (e.g., via diameter and wafer thickness) on the interfacial reliability are elucidated. Furthermore, the effects of via material properties and dielectric buffer layers are discussed.

Increasing demand for new and more advanced electronic products, with smaller form factor and superior functionality and performance, while reducing the cost, has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies. 3D packaging, using z-axis through silicon via (TSV) stacking concept has been and continues to be investigated by many of the semiconductor manufacturers and research institutes and is believed to be one of the most promising, if not the most promising concept that could successfully address the limitations of today's packaging technologies. There is a continuous increase of interest in development and study of applicability of this new chip stacking approach to existing and future devices; currently, more than fifty companies worldwide are involved in some sort of 3D TSV packaging developments. There are several steps involved in 3D chip stacking using TSV technology. Each of these steps requires different techniques, materials and processes, applications that have to be well understood and integrated in order to successfully be applied. This paper will address various electrodeposition processes applied to form 3D interconnects, from TSV deposition, which is the main metallization step that stays at the hearth of this new technology, to other metallization steps for additional connections, such as bumping and redistribution layers, already well known and applied processes in current wafer level packaging (WLP) applications. Advantages and difficulties associated with each of these technologies, with more focus on 3D vertical integration using TSV copper interconnect, including the approaches taken to overcome them, will be presented. Deposition conditions for bumping were optimized in order to enable higher deposition rates. For other through- mask applications, such as redistribution lines (RDL), the complexity of the pattern, deposition rate, chemical formulation and process parameters were found to have a significant effect on within-die (WID) thickness distribution. In case of WLP structures of thick metal and high aspect ratios, seed layer uniformity proved to be essential for achieving void-free deposition. Void-free structures, especially for high aspect ratio vias seeded with dry methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), seem difficult to obtain. New approaches, such as seed layer repair (SLE) or direct on barrier electrodeposition (DOB) can provide superior uniformity and coverage of the conductive layer, necessary for a uniform nucleation of copper electrodeposition process along the entire sidewall of the via, at significantly lower costs. This paper will present TSV structures obtained with wet chemical processes applications for both seed layer and via filling. Besides seed layer uniformity, additional factors were identified to also be critical for successfully filling deep vias. They are: via profile, wettability of vias, superior performance of chemistries and high performance equipment. By selecting the most appropriate deposition methods and optimizing the chemical formulations together with the process parameters, void-free TSV structures can be obtained.

This paper proposes an octagonal layout for enhancing the ability of resisting electromagnetic interference in Through Silicon Via (TSV) array. The influential factors of crosstalk noise between TSVs are investigated, including the TSV pitch, signal and ground TSVs location, and signal types (single-end and differential signal) by using a coplanar wave guide (CPW) testing structure. These results, based on traditional TSV arrays, show that a staggered TSV layout with differential signals had lower crosstalk noise. On this basis, the octagonal layout of TSV array is proposed and we show that it has obvious superiority in reducing occupied silicon area and crosstalk noise. Compared with traditional TSV arrays, the crosstalk noise is almost reduced by 44%. In order to further reduce the silicon area occupied by TSV without worsening crosstalk noise, the new division TSV structure is proposed in which a large TSV was substituted by four smaller TSVs. The area occupied by a single TSV and TSV array are both reduced by 60% without decreasing signal integrity when the regular TSV in the octagonal layout are replaced by a new TSV structure.

This paper presents a micromachined stress-free through silicon via (TSV) backend process for AlGaN/GaN-on-Si (1 1 1) platform-based devices, which was processed by assisted back grinding, chemical mechanical polishing, deep reactive ion etching (DRIE) and copper (Cu) electroplating for the TSV. The metal-filled TSV structure was formed to enhance thermal conduction from the frontend terminal to the backend terminal, especially the source region of the AlGaN/GaN-on-Si (1 1 1) platform-based RF power devices. At the end of a stress-free TSV dry etching process, we have changed RF power 600 W to 300 W to minimize thermal stress of the fabricated TSV electrode pad structure of the AlGaN/GaN-on-Si platform-based devices. Additionally, we have sputtered a multi-metal layer and electroplated Cu metal to interconnect a topside electrode to TSV. To protect the thinned TSV electrode pad structure from water pressure in a sawing process, we have covered photoresist (AZ4330RS) of 3.3 µm thickness on the top area of the structures. We confirmed that the proposed TSV formation method assisted by low-power operation DRIE and protection of the thinned TSV surface by using the thick photoresist is very effective to create minimally stressed TSV structures in AlGaN/GaN-on-Si platform-based devices. The improvement was proved by the yield of dice without bursting the pad structures on a 4 inch AlGaN/GaN-on-Si wafer.

In the present study, high density TSV structures have been designed and fabricated with different diameter and depths, ranging from 2 to 60 µm and 50 to 100 µm respectively. The ratios of TSV diameter to space between TSVs are 1∶2, 1∶3 and 1∶4. Inspection of TSV structures at each processing step is very crucial to proceed to next step. 3D X-ray CT scan analysis has been employed to inspect TSV wafers at different processing steps. Detailed 3D X-ray CT scan analysis has been carried out on 20, 50 and 60 um TSV array structures. Using this method, it is possible to observe defect shape, size and distribution by conducting the virtual cross-section at desired location. Based on the detailed online failure analysis, TSV process development parameter are being fine-tuned and optimized.

Increasing demands for electronic devices with greater functionality, superior performance in more compact and smaller packages has driven the semiconductor industry to develop more advanced packaging technologies. To address the limitations of two-dimensional configuration (2D), which has been the traditional approach to IC integration, in the past few years, new emerging technologies have been developed. Vertical integration proved to be essential in achieving a greater integration flexibility of different technologies, disparate devices, reason for which a general trend of transition from 2D to three-dimensional (3D) integration is currently being observed in the industry [1-5]. Among all the different types of 3D packaging technologies, 3D chip integration using through silicon via (TSV) copper is considered one of the most advanced technologies, and certainly, one of the hottest topics in the industry today. There are different materials and methods that have been proposed and tested for TSV applications. Applicability of each material and method is limited by feature dimensions, final deposit characteristics and process reliability, practicability and last, but not least, cost considerations. Copper electrochemical deposition processes have several characteristics that make them attractive for various semiconductor applications, including TSV structure formation. This paper will address various copper electrodeposition processes applied to form 3D interconnects. Advantages and difficulties associated with each of these technologies and the approaches taken to overcome them will be presented. Reliable WLP structures of thick metal and high aspect ratios seem to be difficult to achieve when dry methods, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) are applied. New approaches, such as seed layer repair (SLE) or direct on barrier electrodeposition (DOB), can provide superior uniformity and coverage of the conductive layer, necessary for a uniform nucleation of copper electrodeposition for deep via filling, at significantly lower costs. TSV structures obtained with such techniques will be reviewed, along with the optimization work performed for achieving super conformal deep-via filling. Applying the optimum process parameters, void free TSV structures over a wide range of feature sizes and aspect ratios can be achieved. The effect of various factors that could considerably affect the performance, manufacturability and cost will be explained. Integrated costs estimations associated with TSV for a viafirst approach, including a breakdown of the process steps will be presented.

In this paper, we design a new program to achieve carbon nanotubes through silicon vias (TSV) interconnects compatible with CMOS technology using an auxiliary TSV structures and laser local heating method. Auxiliary TSV structures are made by two wafers. One wafer is etched into ups and downs structures and then deposited SiN x and SiO 2 film. The other one is made into TSV structures by deep silicon etching, depositing thin film and wafer thinning and polish. Two wafers are bonded together by patterned BCB (Benzocyclobutene). For the entire device structures, we use FDTD solutions software to simulate infrared optical properties of SiN x . SiN x film layer can absorb 10.6 µm infrared laser strongly. Thermal simulation of geometrical model by COMSOL Multiphysics software shows well temperature compatibility. It turns out the program is compatible with current CMOS processes. Using a laser local heating method, we have studied the local growth of carbon nanotubes. Carbon nanotubes grown in TSVs are sparse, intertwined and have a poor morphology; the reason for this is that TSVs' geometric sizes limit gases flows. Carbon nanotubes interconnect still need further study.