1 - The basics

Today, DAW (Digital Audio Workstation) software lies at the heart of music production and has become an indispensable part of the industry. With the advancement of technology, music production is no longer confined to large studios but has also become accessible to individual users. Now, recording, mixing, and mastering processes can be carried out in a home environment using computer-based systems, without the need for expensive equipment. This fully digital workflow is referred to as "in-the-box" production. Technological developments have enabled individuals to produce music at a professional level in home studios, leading to the emergence of digital alternatives to analog devices. Digital processors have begun to replace analog equipment due to their cost-effectiveness and practicality. This study examines the differences between digital signal processors and analog devices in terms of usage, application areas, and sound processing methods. The research aims to compare digital and analog signal processors, particularly focusing on their processing methods, speed, flexibility, quality, and impact on sound. Based on the findings, it is concluded that digital signal processors, which are increasingly replacing analog processors in the music industry, do not possess the same characteristics as their analog counterparts.

10 - Hardware and software development tools

An all-digital positron emission tomography (PET) scanner for imaging small animals has been developed at Huazhong University of Science and Technology (HUST). The implementation of block detector with position sensitive photomultiplier (PSPMT) and multi-voltage threshold (MVT) technology is presented in this paper. The detector comprises 12 basic detector modules (BDMs), which can be used to construct various types of PET scanner architecture due to the modularized design. Each BDM is composed of a detector unit (DU) and a digital processing unit (DPU). The scintillation pulses are obtained in DU, from which the time, energy and position can be derived and processed in DPU by using digital signal processing (DSP) algorithm. Then coincidence data and list-mode data can be obtained in soft singles processing unit (SSPU). We arrange two BDMs as a dual-head PET scanner to evaluate the system. Our results show that the average energy resolution is ∼14%@511keV full-width-at-half-maximum (FWHM) and the coincidence time determination is ∼1.38 ns FWHM. Moreover, the reconstructed image of a homemade micro-Derenzo phantom shows that the rods with a diameter of 1.6mm can be clearly distinguished. The results are promising and demonstrate the potentials of the alldigital PET system.

This paper introduces a technique, called resynchronization, for reducing synchronization overhead in multiprocessor implementations of digital signal processing (DSP) systems. The technique applies to arbitrary collections of dedicated, programmable or configurable processors, such as combinations of programmable DSP's, ASICs, and FPGA subsystems. Thus, it is particularly well-suited to the evolving trend toward heterogeneous single-chip multiprocessors in DSP systems. Resynchronization exploits the well-known observation that in a given multiprocessor implementation, certain synchronization operations may be redundant in the sense that their associated sequencing requirements are ensured by other synchronizations in the system. The goal of resynchronization is to introduce new synchronizations in such a way that the number of original synchronizations that become redundant exceeds the number of new synchronizations that are added, and thus, the net synchronization cost is reduced. Our study is based on the context of self-timed execution for iterative dataflow specifications of DSP applications. An iterative dataflow specification consists of a dataflow representation of the body of a loop that is to be iterated indefinitely; dataflow programming in this form has been employed extensively in the DSP domain.

This paper describes the methodology that utilises some of the ATM traffic analysis techniques in the performance analysis of multichannel digital signal processing (DSP) systems. The analysed multichannel DSP systems employ statistical multiplexing in order to improve the DSP resource utilisation. A case study is used to illustrate the application of the proposed methodology. Performance of the studied system was estimated and it was shown that a significant efficiency gain may be achieved over the DSP systems that do not utilise statistical multiplexing of their resources.

Hereafter, we present an approach aiming to improve the reliability of digital signal processing (DSP) systems operating in real noisy (electromagnetic interference—EMI) environments. The approach is based on the coupling of two techniques: the “DSP-oriented signal integrity improvement” technique deals with increasing the signal-to-noise ratio (SNR) and is essentially a modification of the classic Recovery Blocks Scheme. The second technique, named “SW-based fault handling” aims to detect in real-time data- and control-flow faults throughout modifications of the processor code. When compared to conventional approaches using Fast Fourier Transform (FFT) and Hamming Code, the primary benefit of such an approach is to improve system reliability by means of a considerably low complexity, reasonably low performance degradation and, when implemented in hardware, with reduced area overhead. Aiming to illustrate the proposed approach, we implemented a HW/SW prototype to operate as a speech recognition system (SRS). This prototype was tested under a home-tailored EMI environment according to the IEC 61000-4-29 International Standard Normative. The obtained results indicate that the proposed approach can effectively improve the reliability of DSP systems operating in real noise (EMI) environments.

A low power fuzzy logic based variable resolution ADC for wireless ECG monitoring systems

This paper presents a high-level synthesis methodology which may be applied to the synthesis of bit-serial, digit-serial or bit-parallel digital signal processing (DSP) systems. The methodology accepts as input a DSP system behavioral specification. The methodology provides for the optimization of DSP systems subject to constraints on throughput, IC area, data path width, and resource sharing strategies. The optimization technique is based on a generalized hill climbing algorithm known as simulated annealing. The output is control logic and data path specifications in a device independent hardware description language. Design examples of bit-serial and digit-serial filter realizations synthesized using the methodology are included.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This report delves into the concept of the SIDRA instrument designed for the measurement of energetic fluxes of charged particles in space. It also presents the preliminary laboratory tests results of the breadboard model electronic units. The SIDRA instrument consists of a detector head made of high purity silicon and high performance scintillation detectors, analog and digital signal processing units, and it also includes a secondary power supply module. Preliminary results of Monte Carlo instrument simulation using the CERN GEANT4 tool are presented and the measured key specifications of charge-to-voltage converters, shapers and peak detectors are discussed. Finally, the performance of the digital processing unit with its software and the parameters of the instrument breadboard model, in particular mass, dimensions and power consumption are also presented.

The intense requirements of high-speed implementations of MultiDimensional (MD) Digital Signal Processing (DSP) systems justify the Application Specific Integrated Circuits (ASIC) designs and/or multiprocessor implementations. MD retiming has been recently proposed to improve the circuitry performance in high-level synthesis of single-rate MD DSP systems. This paper has conducted new theoretical analysis of MD multirate DSP systems modeled in data-flow graphs, and proposes intercalation of MD multirate systems so that unified MD retiming operations can be applied on multidimensional multirate DSP systems. By retiming and intercalation, full intra-iteration parallelism is achieved and functional elements can be executed simultaneously on circuits for the generic class of MD multirate DSP systems.KeywordsMultirate Signal ProcessingMD Data Flow GraphMultidimenional Retiming

In this chapter the evolution of analogue sampled-data techniques has been reviewed. The switched-capacitor technique has been seen to dominate in general purpose applications, whilst CCDs are being used extensively in imaging arrays. The emergence of mixed-mode analogue and digital signal processing and the subsequent need to integrate analogue sampled-data circuits on a digital VLSI process was identified. It was then seen that switched capacitors are not fully compatible with digital VLSI technology and that advances in technology will degrade their performance. Finally, the use of switched-current circuits, as a digital process compatible analogue sampled data signal processing technique, has been identified and this forms the basis of this text.

High-speed high resolution analog-to-digital converter (ADC) is the key design blocks in mixed-signal chip design since the ADC is an interface between digital signal processing systems and the analog world. With the rapid advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power ADCs that can be realized in a mainstream deep sub-micrometer CMOS technology. On the other hand, since analog circuits tend to be sensitive to fluctuations in temperature and the fabrication process, circuit designers are forced to allow for a wide margin to ensure the desired operation of all the chips under various conditions. Therefore, if the margins can be minimized, both reduction of power dissipation and a higher yield in mass production can be achieved. To tap onto the waves of the rapid booming wireless communication markets, high resolution and high speed A/D converter is required at very low power consumption. Providing the wanted resolution at the required speed for the minimum power consumption and silicon cost is what's driving the use of specific A/D architectures [1]. Architectures that have been applied include flash, subranging, successive approximation, sigma-delta and pipelined. Each of these architectures has their specific advantages and drawbacks. Pipelined architecture poised as a suitable candidate since the power consumption will be an order of magnitude better comparing to flash ADC, subranging ADC, successive approximation ADC and oversampling ADC. Moreover, a correction algorithm can be employed to compensate for the errors in the sub-ADC. Shooting for even higher speed, parallelism is required to be incorporated into pipelined structure. Hence, in this work, a feasibility study of a novel subranging pipelined A/D converter with 100 MS/s and 8-bit resolution is conducted. This research describes the design of a 8-bit 100 MS/s subranging pipelined analog-to-digital converter(ADC) suitable for wide-range applications. To achieve the wide-range performance, this work purposes a novel architectural design at both system and circuit levels. At the device level, device modeling and active components characterisations are carefully studied. Thin gate oxide, NFET is fabricated in Chartered 90nm CMOS process. The results showed that the models used in SPIC simulation correlate well with the measured results except at the end of high VDD where breakdown is seen in the measured results but not during simulation. At the circuit level, a 3-bit coarse ADC and a 6-bit fine ADC are developed. Logic designs are also carried out. At the system level, this work investigates the effects of ADC design parameters such as DNL and INL in the static DC aspects and SFDR and ENOB in the dynamic AC aspects. A top-down design methodology is adopted in this work. The behavioral modelling results verify the success of the proposed architecture. The simulation results showed that the designed ADC is able to achieve a 7.4 effective bits out of 8 bit resolution.

The object of the study is the procedures for automated design and analysis of digital signal processing algorithms on the SoC technology platform. The subject of the study is models, methods and procedures for designing and optimal selection of SoC components for the implementation of digital signal processing algorithms for audio spectrum. The aim of the study is to develop models and procedures for determining the possibilities of a compromise distribution of signal processing algorithm computations in the cycle of computer-aided design on the SoC technology platform in terms of performance and the feasibility of using hardware and software algorithms realization. The article solves the following tasks: consideration of the procedures for interacting the processor core with programmable logic as part of system-on-chip systems; development of procedures for computer-aided design and analysis of signal processing systems using programming languages and hardware description languages for the implementation of embedded systems. The following methods are being used: implementation of digital signal processing algorithms in the C programming language and high-level synthesis tools for realizing IP blocks, diagnostic experiment by generating test signal patterns, and analysis of the processing results at the system output. The results achieved. Based on the analysis of the procedures for the interaction of the processor core and programmable logic on the selected SoC platform, a model of the audio spectrum signal processing system is designed. The practical implementation was performed based on the Vivado/Vitis/Vitis HLS CAD tool stack. The proposed model was verified using a programmable test signal generator and analyzing the obtained characteristics of digital filters at the system output. Conclusions. The article analyzes the principles of designing embedded information processing systems implemented in system-on-chip. The principles of building and analyzing digital signal processing systems based on system-on-chip containing programmable logic and processor parts are considered. The developed methods have been tested on the algorithms of CIC and FIR filters on the technological platform of SoC FPGA of the ZYNQ-7000 family of Xilinx company.

Describes the design of an interconnection network switch VLSI for parallel digital signal processing (DSP) systems. This VLSI features 6*400 Mb/s bidirectional communication ports and 1.44-Gb/s internal switching capability for realizing efficient packet-switched communication among many processing elements. To achieve this performance with existing CMOS technology, the transport line transfers 8 b in parallel at 50 MHz; input data are first multiplexed up to 64 b and switched at 25 MHz. An automatic routing function is implemented on each switch using a distributed routing table scheme. A high-level behavioral description based CAD (computer-aided design) system called PARTHENON is used to design the functions and logic circuits of this VLSI. The suitability and effectiveness of PARTHENON for switch design are also shown in terms of parallel operation and finite state machine design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper emphasizes on the design of a fully integrated low-power mixed-signal demodulator for multi-gigabit operations in 90 nm CMOS technology. A 3-bit ADC can be used to convert the analog inputs to digital form. But these baseband ADC's experience clipping distortions. This can be reduced by employing wide automatic gain control (AGC). The front-end of the system includes IQ mixers, a QVCO, frequency synthesizer, and AGC. This constitutes the analog block of the demodulator. AGC consists of Variable Gain Amplifier (VGA), power detector circuit, Differential to single ended amplifier and Operational amplifier. 6-bit current steering DAC is used to digitally control the output power of VGA. In order to recover OOK modulated signals, the analog signal processor (ASP) is used. This paper focuses on the design of fully integrated receiver consisting of broadband demodulator with embedded analog and digital signal processors in deep-submicron CMOS technology.