10 - Hardware and software development tools

The rapid increase in digital signal processing (DSP) applications has generated a strong demand for electrical engineers with DSP backgrounds; however, the gap between industry needs and university curricula still exists. To answer this challenge, a sequence of innovative DSP courses that emphasize hands-on experiments and practical applications were developed for continuing education in electrical and computer engineering. These courses are taught in the evening for night-school students having at least three years of work experience. These courses enable students to experiment with sophisticated DSP applications to augment the theoretical, conceptual, and analytical materials provided in traditional DSP courses. The inclusion of both software and hardware developments allows students to undertake a wide range of DSP projects for real-world applications. Assessment data concludes that the digital signal processor fundamentals course can increase learning interest and overcome the prerequisite problem of DSP laboratory experiments. This paper also briefly introduces representative examples of some challenging DSP applications.

This paper introduces a technique, called resynchronization, for reducing synchronization overhead in multiprocessor implementations of digital signal processing (DSP) systems. The technique applies to arbitrary collections of dedicated, programmable or configurable processors, such as combinations of programmable DSP's, ASICs, and FPGA subsystems. Thus, it is particularly well-suited to the evolving trend toward heterogeneous single-chip multiprocessors in DSP systems. Resynchronization exploits the well-known observation that in a given multiprocessor implementation, certain synchronization operations may be redundant in the sense that their associated sequencing requirements are ensured by other synchronizations in the system. The goal of resynchronization is to introduce new synchronizations in such a way that the number of original synchronizations that become redundant exceeds the number of new synchronizations that are added, and thus, the net synchronization cost is reduced. Our study is based on the context of self-timed execution for iterative dataflow specifications of DSP applications. An iterative dataflow specification consists of a dataflow representation of the body of a loop that is to be iterated indefinitely; dataflow programming in this form has been employed extensively in the DSP domain.

The role of software is becoming increasingly important in the implementation of digital signal processing (DSP) applications. As this trend intensifies, and the complexity of applications escalates, we are seeing an increased need for automated tools to aid in the development of DSP software. This paper reviews the state of the art in programming language and compiler technology for DSP software implementation. In particular, we review techniques for high-level block-diagram-based modeling of DSP applications; the translation of block-diagram specifications into efficient C programs using global target-independent optimization techniques; and the compilation of C programs into streamlined machine code for programmable DSP processors using architecture-specific and retargetable back-end optimizations. We also point out important directions for further investigation.

This paper describes the methodology that utilises some of the ATM traffic analysis techniques in the performance analysis of multichannel digital signal processing (DSP) systems. The analysed multichannel DSP systems employ statistical multiplexing in order to improve the DSP resource utilisation. A case study is used to illustrate the application of the proposed methodology. Performance of the studied system was estimated and it was shown that a significant efficiency gain may be achieved over the DSP systems that do not utilise statistical multiplexing of their resources.

This paper presents a high-level synthesis methodology which may be applied to the synthesis of bit-serial, digit-serial or bit-parallel digital signal processing (DSP) systems. The methodology accepts as input a DSP system behavioral specification. The methodology provides for the optimization of DSP systems subject to constraints on throughput, IC area, data path width, and resource sharing strategies. The optimization technique is based on a generalized hill climbing algorithm known as simulated annealing. The output is control logic and data path specifications in a device independent hardware description language. Design examples of bit-serial and digit-serial filter realizations synthesized using the methodology are included.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hereafter, we present an approach aiming to improve the reliability of digital signal processing (DSP) systems operating in real noisy (electromagnetic interference—EMI) environments. The approach is based on the coupling of two techniques: the “DSP-oriented signal integrity improvement” technique deals with increasing the signal-to-noise ratio (SNR) and is essentially a modification of the classic Recovery Blocks Scheme. The second technique, named “SW-based fault handling” aims to detect in real-time data- and control-flow faults throughout modifications of the processor code. When compared to conventional approaches using Fast Fourier Transform (FFT) and Hamming Code, the primary benefit of such an approach is to improve system reliability by means of a considerably low complexity, reasonably low performance degradation and, when implemented in hardware, with reduced area overhead. Aiming to illustrate the proposed approach, we implemented a HW/SW prototype to operate as a speech recognition system (SRS). This prototype was tested under a home-tailored EMI environment according to the IEC 61000-4-29 International Standard Normative. The obtained results indicate that the proposed approach can effectively improve the reliability of DSP systems operating in real noise (EMI) environments.

The intense requirements of high-speed implementations of MultiDimensional (MD) Digital Signal Processing (DSP) systems justify the Application Specific Integrated Circuits (ASIC) designs and/or multiprocessor implementations. MD retiming has been recently proposed to improve the circuitry performance in high-level synthesis of single-rate MD DSP systems. This paper has conducted new theoretical analysis of MD multirate DSP systems modeled in data-flow graphs, and proposes intercalation of MD multirate systems so that unified MD retiming operations can be applied on multidimensional multirate DSP systems. By retiming and intercalation, full intra-iteration parallelism is achieved and functional elements can be executed simultaneously on circuits for the generic class of MD multirate DSP systems.KeywordsMultirate Signal ProcessingMD Data Flow GraphMultidimenional Retiming

The current trends of advancement of memory technology indicates reasonable scope to have efficient memory-based computing systems as promising alternative to the conventional logic-only computing in order to meet the stringent constraints and growing requirements of the digital signal processing (DSP) systems in widely varying application environments. Several algorithms and architectures have been suggested in the literature to reduce the area- and time-complexities of commonly encountered computation-intensive cores of DSP functions by memory-based computing, but many more novel algorithms and architectures need to be developed to design flexible area-delay-power-efficient systems for various DSP applications.

This paper presents the use of the viciLogic viciLab tool suite for prototyping of audio digital signal processing (DSP) hardware on remote or locally connected PYNQ Systems on Chip (SoCs), along with flexible computer control software interfaces. The tool suite enables rapid prototyping of DSP hardware components, including demonstration, control and visualisation of components on local or remote hardware. Hardware components can be developed directly in existing hardware description languages (HDLs) or using higher-level design interfaces such as MathWorks HDL coder. Two configurable software control interfaces are presented: a low-level console builder facilitating fast graphical user interface (GUI) creation for hardware interaction, along with script-based automation; and a high-level Python-based GUI console creator integrates audio sampling, automated DSP hardware effect selection and SoC control, audio streaming and playback, and real-time waveform graphing. The two interfaces presented in this paper are illustrated through a series of DSP examples of increasing complexity: 8- and 16-tap FIR filters (with user-created VHDL model source); distortion and tremolo DSP functions (developed MathWorks HDL coder VHDL model source); and combinations of these components.

The authors introduce a parallel DSP (digital signal processing) system called NOVI, consisting of 36 processor nodes. NOVI has a multicomputer architecture, which provides high programmability and effective scheduling capability. Its program-development-assist system facilitates powerful debugging functions to observe all states of NOVI and to control its execution. Each processor node comprises a transputer, a floating-point ALU (arithmetic logic unit), and 1 Mbyte of local memory, which can deal with even rather large tasks within a single node. An interconnection board allows easy reconfiguration into various network topologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Energy consumption in Digital Signal Processing (DSP) application is a vital parameter of consideration. Mostly DSP applications deplete power. Battery constraint is important in many mobiles, processors, and sensor-related devices. The major critical operations in DSP architecture are multiplication and addition. Multiplication process is performed using repetitive addition. Hence, adder is the basic component used in digital signal processor. DSP architecture is proposed with the energy-efficient goal. Traditional carry select adder contains ripple carry adder block is replaced by parallel prefix adder. By replacing that block and introducing folded tree, we can reduce power used by DSP processors. This architecture can be used in all power constrained DSP applications. In the existing system, folded tree is used in architecture to reduce the number of processing elements, and they used carry look-ahead adder to perform the internal processing element operations. In the proposed system, carry look-ahead adder is replaced by LFA and PA to harness the energy depleted in an application (e.g., DSP application). Power consumption is reduced by 12–15% as compared with the existing algorithms using Cyclone III (EP3C16F484C6).

This paper describes the development and application of a modular digital signal processing (DSP) system using the 2101 analog devices processor. Two noncontact applications are described: the measurement of pipe cross-sections and 3D measurement using multiple camera views.

Finite Impulse Response (FIR) Filter occupied a significant position in most of Digital Signal Processing (DSP) Applications. The behaviour of FIR filters can be realized in software for DSP applications and executed on Digital Signal Processor architectures. These kinds of digital filters consider digital components, digital input and perform mathematical computations to produce digital output. In modern DSP applications demanding area efficient architecture for DSP algorithms while optimizing throughput. This can be achieved by design of hardware architectures for DSP algorithms and apply design optimization techniques to accelerate the throughput and minimize area. This article attempts to develop hardware architectures for FIR Filter and apply the design optimization techniques present in literature. In this article, High Level Synthesis concepts were adapted to develop hardware architecture for FIR filter and optimization techniques have been applied to optimize design attributes like area, throughput and power. Finally, design attributes are summarized after applying optimization techniques and published significant architectural attributes suitable for real life DSP applications.

Finite impulse response (FIR) digital filters are key components used in many digital signal processing (DSP) systems because of their linear phase, stability, fewer finite precision errors and regular structure. The real time realization of FIR filter with less hardware requirement and less latency has become very critical with increasing developments in very large scale integration (VLSI) technology. The objective of this paper to explore the current trends in the development of algorithms and architectures for memory based realization of FIR filters that are mainly concerned with reducing the overall area-delay-power complexities. The purpose of this study is to compare these architectures based on ROM size, delay and throughput. The results presented here would assist the researchers in the field of Digital Signal processing to select best architecture for an application based on requirements. New algorithms and architectures need to be developed to design area-delay-power-efficient FIR filters for various demanding DSP applications.

International audience