A modular DSP system for use in embedded electro-optical applications

10 - Hardware and software development tools

Energy consumption in Digital Signal Processing (DSP) application is a vital parameter of consideration. Mostly DSP applications deplete power. Battery constraint is important in many mobiles, processors, and sensor-related devices. The major critical operations in DSP architecture are multiplication and addition. Multiplication process is performed using repetitive addition. Hence, adder is the basic component used in digital signal processor. DSP architecture is proposed with the energy-efficient goal. Traditional carry select adder contains ripple carry adder block is replaced by parallel prefix adder. By replacing that block and introducing folded tree, we can reduce power used by DSP processors. This architecture can be used in all power constrained DSP applications. In the existing system, folded tree is used in architecture to reduce the number of processing elements, and they used carry look-ahead adder to perform the internal processing element operations. In the proposed system, carry look-ahead adder is replaced by LFA and PA to harness the energy depleted in an application (e.g., DSP application). Power consumption is reduced by 12–15% as compared with the existing algorithms using Cyclone III (EP3C16F484C6).

The rapid increase in digital signal processing (DSP) applications has generated a strong demand for electrical engineers with DSP backgrounds; however, the gap between industry needs and university curricula still exists. To answer this challenge, a sequence of innovative DSP courses that emphasize hands-on experiments and practical applications were developed for continuing education in electrical and computer engineering. These courses are taught in the evening for night-school students having at least three years of work experience. These courses enable students to experiment with sophisticated DSP applications to augment the theoretical, conceptual, and analytical materials provided in traditional DSP courses. The inclusion of both software and hardware developments allows students to undertake a wide range of DSP projects for real-world applications. Assessment data concludes that the digital signal processor fundamentals course can increase learning interest and overcome the prerequisite problem of DSP laboratory experiments. This paper also briefly introduces representative examples of some challenging DSP applications.

Finite Impulse Response (FIR) Filter occupied a significant position in most of Digital Signal Processing (DSP) Applications. The behaviour of FIR filters can be realized in software for DSP applications and executed on Digital Signal Processor architectures. These kinds of digital filters consider digital components, digital input and perform mathematical computations to produce digital output. In modern DSP applications demanding area efficient architecture for DSP algorithms while optimizing throughput. This can be achieved by design of hardware architectures for DSP algorithms and apply design optimization techniques to accelerate the throughput and minimize area. This article attempts to develop hardware architectures for FIR Filter and apply the design optimization techniques present in literature. In this article, High Level Synthesis concepts were adapted to develop hardware architecture for FIR filter and optimization techniques have been applied to optimize design attributes like area, throughput and power. Finally, design attributes are summarized after applying optimization techniques and published significant architectural attributes suitable for real life DSP applications.

This paper introduces a technique, called resynchronization, for reducing synchronization overhead in multiprocessor implementations of digital signal processing (DSP) systems. The technique applies to arbitrary collections of dedicated, programmable or configurable processors, such as combinations of programmable DSP's, ASICs, and FPGA subsystems. Thus, it is particularly well-suited to the evolving trend toward heterogeneous single-chip multiprocessors in DSP systems. Resynchronization exploits the well-known observation that in a given multiprocessor implementation, certain synchronization operations may be redundant in the sense that their associated sequencing requirements are ensured by other synchronizations in the system. The goal of resynchronization is to introduce new synchronizations in such a way that the number of original synchronizations that become redundant exceeds the number of new synchronizations that are added, and thus, the net synchronization cost is reduced. Our study is based on the context of self-timed execution for iterative dataflow specifications of DSP applications. An iterative dataflow specification consists of a dataflow representation of the body of a loop that is to be iterated indefinitely; dataflow programming in this form has been employed extensively in the DSP domain.

The current trends of advancement of memory technology indicates reasonable scope to have efficient memory-based computing systems as promising alternative to the conventional logic-only computing in order to meet the stringent constraints and growing requirements of the digital signal processing (DSP) systems in widely varying application environments. Several algorithms and architectures have been suggested in the literature to reduce the area- and time-complexities of commonly encountered computation-intensive cores of DSP functions by memory-based computing, but many more novel algorithms and architectures need to be developed to design flexible area-delay-power-efficient systems for various DSP applications.

The aim of this contribution is first to show how the Szego theory of orthogonal polynomials on the unit circle is intimately related to the celebrated Levinson algorithm, which is commonly used in digital signal processing (DSP) applications to solve various least-squares problems. A computationally more efficient substitute for the Levinson algorithm, termed the split Levinson algorithm, has recently been proposed in the DSP literature. In the case of real data, this new algorithm can be interpreted naturally in the framework of a well-defined one-to-one correspondence between the families of real Szego polynomials and the families of polynomials orthogonal on the interval [-1, 1] with respect to a symmetric measure. More generally, the philosophy underlying the split Levinson algorithm opens the door to an interesting “tridiagonal approach” to the theory of complex Szego polynomials, nonnegative definite Hermitian Toeplitz matrices, and related algebraic and function theoretic questions. Some of the main topics of this new mathematical framework are briefly reviewed and are shown on specific examples to be of particular interest in DSP applications.

Signal processing has always been a critical aspect of interferometric spectroscopy. The main value of Fourier Transform Spectroscopy (FTS) is to provide the maximum information per unit time. This means that careful signal processing is required to maximize the signal to noise ratio of the result. Digital signal processing (DSP) is not new in FTS. DSP for apodization, Fourier transform, phase correction, and some digital filtering have been used for many years. The first difficulty encountered in using DSP is the required transformation of the continuous time signal to a sequence of finite precision numbers, that is a discrete time, discrete magnitude representation of the continuous signal. Today, sampling and digitization with conventional techniques are reasonably straightforward, with digitization noise of the order of 2−16. Advances in several aspects of FTS technology, including step scanning, have created the need to lower the digitization noise. The processing of signals from multiple modulation FTS experiments, specially step-scan signals, has presented serious limitations until recently, due primarily to the performance restrictions of the available hardware, and the fundamental limitations of the analog systems used. The application of DSP techniques to reduce the sampling and digitization errors are reviewed, and practical solutions that can provide digitization noise lower than 2−24 with low cost systems are described. Some of the causes and effects of sampling error are reviewed, to clarify common misunderstandings. DSP applications in the detection of multiple modulation step-scan experiments and photoacoustic spectroscopy are described in detail. These applications allow the measurement of the signal during the entire step time, eliminate interference of secondary effects of phase modulation, and integrate the entire experiment in the data system, eliminating all the analog adjustments (knobs) needed when lock-in amplifiers are used.

This paper describes the methodology that utilises some of the ATM traffic analysis techniques in the performance analysis of multichannel digital signal processing (DSP) systems. The analysed multichannel DSP systems employ statistical multiplexing in order to improve the DSP resource utilisation. A case study is used to illustrate the application of the proposed methodology. Performance of the studied system was estimated and it was shown that a significant efficiency gain may be achieved over the DSP systems that do not utilise statistical multiplexing of their resources.

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).

In this paper presents an efficient table lookup algorithm for high-throughput decoding of the (71, 36, 11) Quadratic Residue (QR) code. The main ideas behind this decoding technique are based on one-to-one mapping between the syndromes S1 and correctable error patterns. As compared with the binary lookup table method, the presented technique is faster than binary searching method for finding error pattern. In addition, it has the advantage that only the operations of addition over a Finite Field are used for decoding QR codes. Moreover, the presented high speed of the decoding procedure has potential applications in modern communication systems and digital signal processing (DSP) systems.

Hereafter, we present an approach aiming to improve the reliability of digital signal processing (DSP) systems operating in real noisy (electromagnetic interference—EMI) environments. The approach is based on the coupling of two techniques: the “DSP-oriented signal integrity improvement” technique deals with increasing the signal-to-noise ratio (SNR) and is essentially a modification of the classic Recovery Blocks Scheme. The second technique, named “SW-based fault handling” aims to detect in real-time data- and control-flow faults throughout modifications of the processor code. When compared to conventional approaches using Fast Fourier Transform (FFT) and Hamming Code, the primary benefit of such an approach is to improve system reliability by means of a considerably low complexity, reasonably low performance degradation and, when implemented in hardware, with reduced area overhead. Aiming to illustrate the proposed approach, we implemented a HW/SW prototype to operate as a speech recognition system (SRS). This prototype was tested under a home-tailored EMI environment according to the IEC 61000-4-29 International Standard Normative. The obtained results indicate that the proposed approach can effectively improve the reliability of DSP systems operating in real noise (EMI) environments.

The intense requirements of high-speed implementations of MultiDimensional (MD) Digital Signal Processing (DSP) systems justify the Application Specific Integrated Circuits (ASIC) designs and/or multiprocessor implementations. MD retiming has been recently proposed to improve the circuitry performance in high-level synthesis of single-rate MD DSP systems. This paper has conducted new theoretical analysis of MD multirate DSP systems modeled in data-flow graphs, and proposes intercalation of MD multirate systems so that unified MD retiming operations can be applied on multidimensional multirate DSP systems. By retiming and intercalation, full intra-iteration parallelism is achieved and functional elements can be executed simultaneously on circuits for the generic class of MD multirate DSP systems.KeywordsMultirate Signal ProcessingMD Data Flow GraphMultidimenional Retiming

Digital Signal Processing (DSP) applications in Bioinformatics have received great attention in recent years, where new effective methods for genomic sequence analysis, such as the detection of coding regions, have been developed. The use of DSP principles to analyze genomic sequences requires defining an adequate representation of the nucleotide bases by numerical values, converting the nucleotide sequences into time series. Once this has been done, all the mathematical tools usually employed in DSP are used in solving tasks such as identification of protein coding DNA regions, identification of reading frames, and others. In this article we present an overview of the most relevant applications of DSP algorithms in the analysis of genomic sequences, showing the main results obtained by using these techniques, analyzing their relative advantages and drawbacks, and providing relevant examples. We finally analyze some perspectives of DSP in Bioinformatics, considering recent research results on algebraic structures of the genetic code, which suggest other new DSP applications in this field, as well as the new field of Genomic Signal Processing.

This work presents an analysis of power efficiency in microprocessor architectures targeting wide-range digital signal processing (DSP) applications. We defined a circuit level power estimation technique based on the integration of traditional analytical power models so as to account for both block-internal and interconnects-dependent dissipation and we extended it to provide applicability to specific DSP-related structures. We applied the modeling approach to several architecture schemes and demonstrated that a relatively novel solution, namely the transfer triggered architecture, can be the most power-efficient scheme in DSP applications.