Design and implementation of efficient multiplier using vedic mathematics

Multi‐dimensional Discrete Fourier Transforms (DFTs) play an important role in signal and image processing applications. Image reconstruction is a key component in signal processing applications like medical imaging, computer vision, face recognition etc. Two dimensional fast Fourier Transform (2D FFT) and Inverse FFT plays vital role in reconstruction. In this paper we present a fast 64 × 64 point 2D FFT architecture based on radix‐43 algorithm using a parallel unrolled radix‐4 3 FFT as the basic block. Our radix‐4 3 architecture is a memory optimized parallel architecture which computes 64‐point FFT, with least execution time. Proposed architecture produces reordered output of both 64‐point one dimensional (1D) FFT and 64 × 64 point 2D FFT, without using any additional hardware for reordering. The proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz and area of 0.841 mm 2 . The power consumption of proposed architecture is 358 mW at 500 MHz. Energy efficiency (FFTs computed per unit of energy) is 341 points/Joule. Computation time of 64 × 64 point FFT is 8.19 μs. ASIC implementation results shows better performance of proposed work in terms of computation time when compared with state‐of‐art implementation. Proposed architecture has also been implemented in Virtex‐7 FPGA which gives comparable area.

Many of today's most popular consumer electronics products rely, to some extent, on Digital Signal Processing (DSP) algorithms and chips. The development of this course had the primary goal of educating students outside electrical engineering about some basic signal processing concepts and applications. For this reason, the focus of the course is on the breadth of applications and includes some hands-on experiments to emphasize important concepts. A secondary goal of the course, through the presentation of many different applications, is to allow students to think about new applications in their fields of study. By completing a project at the end of the course, students have an opportunity to explore in more depth an existing/novel application of signal processing.

There is a dearth of high quality reconfigurable hardware for DWT which can be extensively used in various real time signal and image processing applications. In this article, we have focused on proposing a dedicated customizable hardware for DWT applicable to 1D/2D signal processing. We have proposed bit-serial Distributed Arithmetic (DA) based VLSI architectures for ID/2D DWT. Exploitation of DA enables us to make our designs Multiplierless, thereby consuming less area. Bit serial configuration of DA is also exploited to introduce modularity and pipelining in the proposed convolution DWT based ID/2D architectures. Though the speed of the proposed designs may not be suitable for certain applications, a number of parallel channels can be introduced for the same. The provision of mode selection can efficiently be used to realize 9/7 and also 5/3 DWT filters in the same proposed architecture. In the proposed 1D/2D architecture, we have achieved about 50% memory size reduction, 30% reduction in area consumption and comparable speed in comparison to the other latest notable DWT architecture so far. We have verified the viability of our proposed 2D architecture by utilizing it in real time image decomposition.

In most of the digital signal processing (DSP) applications the critical operations are the multiplication and accumulation. Real-time signal processing requires high speed and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which is always a key to achieve a high performance digital signal processing system. In this paper, design of MAC unit is proposed. The multiplier used inside the MAC unit is based on the Sutra "Urdhva Tiryagbhyam" (Vertically and Cross wise) which is one of the Sutras of Vedic mathematics. Vedic mathematics is mainly based on sixteen Sutras and was rediscovered in early twentieth century. In ancient India, this Sutra was traditionally used for decimal number multiplications within less time. The same concept is applied for multiplication of binary numbers to make it useful in the digital hardware. Here, the coding is done in VHDL and synthesis is done in Xilinx ISE series. The combinational delay obtained after synthesis is compared with the performance of the "Modified Booth Wallace Multiplier" and "High speed Vedic multiplier" presented by Ramesh Pushpangadam. Our proposed Vedic multiplier seems to have better performance.

Chapter 7 - Applications

Discrete Fourier transform (DFT) has many applications in digital signal and image processing and other scientific and technological domains, but its time complexity of direct computation is O(n2), limiting greatly its application range. Thus many people have developed fast Fourier transform (FFT) algorithms, reducing the complexity from O(n2) to O(nlogn)(In this paper logn denotes log2n).But for large n, O(nlogn) is still very high. So multiprocessor systems have been used to speed up the computation of DFT. This paper first introduces a new general method to deduce FFT algorithms, then transforms the deduced second radix-2 decimation-in-time FFT algorithm into another parallelizable sequential form, and finally transforms the latter algorithm into a new parallel FFT algorithm, reducing the time complexity of DFT to O(nlogn/p) (where p is the number of processors). Using similar methods, the authors can also design other new parallel 1-D and 2-D FFT algorithms.

The 16 papers in this special issue focus on adaptive sparse representation of data and applications in signal and image processing.

Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. Thus, for the design of an efficient arithmetic unit, the key functioning elements are multipliers, adders, and the basic logic gates for which the performance parameters which decide the complete performance of the arithmetic unit are area, power dissipation, and speed. Research has been going through the past few decades to design efficient VLSI arithmetic circuits by using logic optimization and circuit optimization techniques to further reduce area, power, and delay. The multiplier design which is initially developed for area optimizations is an array multiplier in which the main disadvantage is the worst-case delay. To overcome this disadvantage, many methodologies came into existence in which Vedic methodology has acquired prominence because of fast computations. It has been found that Vedic multiplier adopting Urdhva Tiryagbhyam is one of the most effective multipliers with minimum delay for multiplication of all types of numbers, either large or small. Though the speed of this multiplier is high, area occupancy is more. Thus, Binary to Excess-one Converter (BEC) technique is employed in this multiplier to reduce area. To further improve the performance, a 16 × 16 Vedic multiplier employing BEC adders and modified logic gates is developed and coded in Verilog HDL and further synthesized using Vivado 2017.2. Synthesis results disclose that the 16-bit Vedic multiplier using BEC technique employing Modified AND gate and Modified OR gate architecture accomplishes power savings of 0.13% compared to a Vedic multiplier using BEC technique. KeywordsVedic multiplierUrdhva tiryagbhyamBEC techniqueModified logic gates

A VLSI implementation of a unified algorithm with the capability of computing all the common arithmetic operations, including division, square rooting etc. and most trigonometric functions, is described. The processor has been designed in 3 μm CMOS technology such that when organised in a pipeline array it can achieve computation rates equivalent to 50 ns, suitable for most real-time signal and image processing applications.

In this article, we present and analyze a new family of fixed-point data formats for signal processing applications. These formats represent compressed two's complement data formats where compression on the sign bit is undertaken on a sample by sample basis. The extra room provided by sign-bit compression is utilized to retain more bits of precision for each individual sample. Compressed two's complement data formats are shown to provide greater dynamic range and improved noise performance over traditional fixed-point data formats such as sign-magnitude, offset binary, and traditional two's complement. Traditional two's complement is shown to be a member of the compressed two's complement family where the compression factor (CF) is equal to one. The dynamic range of a compressed two's complement data format is shown to approach the dynamic range of a non compressed data format raised to the power of the CF. Improved performance for digital signal processing (DSP) applications such as digital filters and transforms is presented for specific instances of this family.

Floating-point arithmetic is enhancive for the realization of a vast application of Digital Signal Processing (DSP) such as Fast Fourier Transform, Discrete Cosine Transform. In this paper, architecture of floating point adder and floating point Subtractor were compared with their fused counterpart known as Fused Addition-Subtract Unit. Since, most of the DSP algorithms require FFT and DCT in their structures hence analysis and implementation were done specifically for complex addition and subtraction involved in FFT computation. Butterfly unit consisting of arithmetic operations like additions, subtractions and multiplications of complex valued data were first implemented using conventional single precision floating point adder and Subtractor. Thereafter, single compressed structure for floating point addition-subtraction was implemented using Verilog HDL. After simulation run on Xilinx ISE tool, it was observed that fused Add-Sub FPU provides better latency results compared to conventional FPU.

Floating-point arithmetic is ever-present in computer systems. All most all computer languages has supports a floating-point number types. Most of the computer compilers called upon floating-point algorithms from time to time for execution of the floating-point arithmetic operations and every operating system must be react virtually for floating-point exceptions like underflow and overflow. The double-precision floating arithmetic is mainly used in the digital signal processing (filters, FFTs) applications, numerical applications and scientic applications. The double-precision floating arithmetic operations are the addition, the subtraction, the multiplication, and the division. Among the all arithmetic operations, multiplication is widely used and most complex arithmetic operation. The double-precision (64-bit) floating point number is divide into three fields, Sign field, Exponent field and Mantissa field. The most significant bit of the number is a sign field and it is a 1-bit length, next 11-bits represents the exponent field of the number and remaining 52-bits are represents the mantissa field of the number. The double-precision floating-point multiplier requires a large 52×52 mantissa multiplications. The performance of the double-precision floating number multiplication mainly depends on the area and speed. The proposed work presents a novel approach to decrease this huge multiplication of mantissa. The Urdhva Tiryagbhyam technique permits to using a smaller number of multiplication hardware compared to the conventional method. In traditional method adding of the partial products are separately done and it takes more time in comparison with the proposed method. In proposed method the partial products are concurrently added with the multiplication operaton and it can reduce the time delay. The double-precision floating multiplier is implemented using Verilog HDL with Xilinx ISE tools on Virtex-5 FPGA.

Signal processing has always been a critical aspect of interferometric spectroscopy. The main value of Fourier Transform Spectroscopy (FTS) is to provide the maximum information per unit time. This means that careful signal processing is required to maximize the signal to noise ratio of the result. Digital signal processing (DSP) is not new in FTS. DSP for apodization, Fourier transform, phase correction, and some digital filtering have been used for many years. The first difficulty encountered in using DSP is the required transformation of the continuous time signal to a sequence of finite precision numbers, that is a discrete time, discrete magnitude representation of the continuous signal. Today, sampling and digitization with conventional techniques are reasonably straightforward, with digitization noise of the order of 2−16. Advances in several aspects of FTS technology, including step scanning, have created the need to lower the digitization noise. The processing of signals from multiple modulation FTS experiments, specially step-scan signals, has presented serious limitations until recently, due primarily to the performance restrictions of the available hardware, and the fundamental limitations of the analog systems used. The application of DSP techniques to reduce the sampling and digitization errors are reviewed, and practical solutions that can provide digitization noise lower than 2−24 with low cost systems are described. Some of the causes and effects of sampling error are reviewed, to clarify common misunderstandings. DSP applications in the detection of multiple modulation step-scan experiments and photoacoustic spectroscopy are described in detail. These applications allow the measurement of the signal during the entire step time, eliminate interference of secondary effects of phase modulation, and integrate the entire experiment in the data system, eliminating all the analog adjustments (knobs) needed when lock-in amplifiers are used.

Signal processing had a significant impact on the development of many elements of modern life, including telecommunications, education, healthcare, industry, and security. The semiconductor industry is the primary driver of signal processing innovation, producing ever-more sophisticated electronic devices and circuits in response to global demand. In addition, the central processing unit (CPU) is described as the “brain” of a computer or all electronic devices and signal processing. CPU is a critical electronic device that includes vital components such as memory, multiplier, adder, etc. Also, one of the essential components of the CPU is the arithmetic and logic unit (ALU), which executes the arithmetic and logical operations within all types of CPU operations, such as addition, multiplication, and subtraction. However, delay, occupied areas, and energy consumption are essential parameters in ALU circuits. Since the recent ALU designs experienced problems like high delay, high occupied area, and high energy consumption, implementing electronic circuits based on new technology can significantly boost the performance of entire signal processing devices, including microcontrollers, microprocessors, and printed devices, with high-speed and low occupied space. Quantum dot cellular automata (QCA) is an effective technology for implementing all electronic circuits and signal processing applications to solve these shortcomings. It is a transistor-less nanotechnology being explored as a successor to established technologies like CMOS and VLSI due to its ultra-low power dissipation, high device density, fast operating speed in THz, and reduced circuit complexity. This research proposes a ground-breaking ALU that upgrades electrical devices such as microcontrollers by applying cutting-edge QCA nanotechnology. The primary goal is to offer a novel ALU architecture that fully utilizes the potential of QCA nanotechnology. Using a new and efficient approach, the fundamental gates are skillfully utilized with a coplanar layout based on a single cell not rotated. Furthermore, this work presents an enhanced 1-bit and 2-bit arithmetic logic unit in quantum dot cellular automata. The recommended design includes logic, arithmetic operations, full adder (FA) design, and multiplexers. Using the powerful simulation tools QCADesigner, all proposed designs are evaluated and verified. The simulation outcomes indicates that the suggested ALU has 42.48 and 64.28% improvements concerning cell count and total occupied area in comparison to the best earlier single-layer and multi-layer designs.

PrefaceThis issue of Proceedings gathers the papers presented at 2019 4th International Conference on Intelligent Computing and Signal Processing (ICSP 2019) held in Xi’an, China during March 29-31, 2019. ICSP 2019 is an international conference covering research and development in the field of intelligent computing and signal processing and participation from all over the world.More than 400 papers were finally accepted after a double blinded peer review process by international reviewers and academic committee members. Divided into 4 chapters, the papers provide a wide spectrum of researches on wide range of intelligent computing and signal processing. The chapters are devoted to Algorithm and Data Mining, Signal and Image Processing, Automation Engineering and Intelligent Application, Computer Modeling and Performance Structure. Specific research results by conference participants were presented and examined in the light of the frameworks outlined above, which is of interest to academics, researchers and professionals in this field.Two keynote speeches were presented from Prof. Weihua Zhuang, University of Waterloo, Canada, whose topic was about Service Provisioning in 5G Communication Networks; Prof. Nagula Sangary, University of Waterloo & Prudential Technology Ltd., whose topic was about Trends and Challenges in Terrestrial Satellite Wireless Communication Systems in mm-Wave range. All the talks were very impressive for the high level of professionalism, and in many cases original ideas and activities have been accomplished or proposed.List of Committees are availble in this PDF.